SLUSE50 November   2023 TPS92642-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal Regulator
      2. 6.3.2  Buck Converter Switching Operation
      3. 6.3.3  Bootstrap Supply
      4. 6.3.4  Switching Frequency and Adaptive On-Time Control
      5. 6.3.5  Minimum On-Time, Off-Time, and Inductor Ripple
      6. 6.3.6  LED Current Regulation and Error Amplifier
      7. 6.3.7  Start-Up Sequence
      8. 6.3.8  Analog Dimming and Forced Continuous Conduction Mode
      9. 6.3.9  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      10. 6.3.10 Pulse Duty Cycle Limit Circuit
      11. 6.3.11 Output Short and Open-Circuit Faults
      12. 6.3.12 Overcurrent Protection
      13. 6.3.13 Thermal Shutdown
      14. 6.3.14 Fault Indicator and Diagnostics Summary
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Duty Cycle Considerations
      2. 7.1.2  Switching Frequency Selection
      3. 7.1.3  LED Current Programming
      4. 7.1.4  Inductor Selection
      5. 7.1.5  Output Capacitor Selection
      6. 7.1.6  Input Capacitor Selection
      7. 7.1.7  Bootstrap Capacitor Selection
      8. 7.1.8  Compensation Capacitor Selection
      9. 7.1.9  Input Dropout and Undervoltage Protection
      10. 7.1.10 Pulse Duty Cycle Limit Circuit
      11. 7.1.11 Protection Diodes
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Calculating Duty Cycle
        2. 7.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 7.2.2.3 Minimum Switching Frequency
        4. 7.2.2.4 LED Current Set Point
        5. 7.2.2.5 Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Compensation Capacitor Selection
        9. 7.2.2.9 VIN Dropout Protection and PWM Dimming
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Compact Layout for EMI Reduction
          1. 7.4.1.1.1 Ground Plane
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.10 Pulse Duty Cycle Limit Circuit

The TPS92642-Q1 features an internal analog circuit to impose a limit on the on-time, tPWN(ON) and off-time, tPWM(OFF), of the output current, ILED. As illustrated in Figure 6-7, the device is controlled by external UDIM pulses with widths less than tPWM_ON(LMT). Any external UDIM pulses that are longer than tPWM(LMT) are truncated to maintain a maximum fixed duty ratio of DPLMT. The device also rejects any spurious pulses that can be present on the external UDIM input by blanking the UDIM signal during the PLMT off time. The off time is a function of the period, tPLMT, set by the external capacitor, CPLMT. This mechanism is designed to help limit overexposure to infrared lights due to error conditions in DMS applications. The relationship between tPLMT, tPWM_ON(LMT) and DPLMT is given in Equation 10.

Equation 10. t P W M _ O N ( L M T ) = D P L M T × t P L M T
GUID-20220606-SS0I-78SR-QR1C-DSN2TJG19V3Q-low.svg Figure 6-7 Duty Cycle Limit Function Using Internal Pulse Generator

The desired pulse period, tPLMT, is set by external capacitor, CPLMT.

Equation 11. t P L M T = 1.168 × 10 5 × C P L M T

The maximum pulse on-duration, tPWM_ON(LMT), and minimum off-duration, tPWM_OFF(LMT), is given in Equation 12 and Equation 13.

Equation 12. t P W M _ O N ( L M T ) = 0.6931 × R P L M T ( P U ) × C P L M T
Equation 13. t P W \M _ O F F ( L M T ) = 1.1 × R P L M T ( P D ) × C P L M T

For LED current set point greater than 2.5 A, the maximum pulse-duration is impacted due to the switching noise in the system. The maximum pulse-duration as a function of LED current is given in Equation 14. Because the off-duration, tOFF, does not change, the duty cycle ratio reduces with increase in LED current.

Equation 14. t P W M _ O N ( L M T ) = 0.6931 × R P L M T ( P U ) × C P L M T - 1.76 × 10 - 2 × I L E D - 2.5 × t P L M T

As an alternative, the PLMT pin can be externally driven by an external pulse generator or microcontroller to set the maximum on-duration and minimum off-duration, independent of the external UDIM input. In this case, the circuit functionality remains unchanged, however ,the pulse parameters are set by external pulse signal driving PLMT pin. The relationship between external PLMT signal and UDIM signal is shown in the following figure.

GUID-20220607-SS0I-1TB2-HTC1-NFMBFJDHSBQP-low.svg Figure 6-8 Duty Cycle Limit Function Using External Pulse Generator

The pulse duty cycle limit function is disabled by connecting PLMT pin to GND. The LED current is controlled directly by the PWM signal connected to UDIM input.