SLVSFR3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPSI2140-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. The TPSI2140-Q1 uses TI's high reliability capacitive isolation technology in combination with internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply.

The primary side of the device is powered by only 9 mA of input current and incorporates a fail-safe EN pin preventing any possibility of back powering the VDD supply. In most applications, the VDD pin of the device should be connected to a system supply between 5 V–20 V and the EN pin of the device should be driven by a GPIO output with logic HI between 2.1 V–20 V. In other applications, The VDD and EN pins could be driven together directly from the system supply or from a GPIO output. All control configurations of the TPSI2140-Q1 do not require additional external components such as a resistor and/or low side switch that are typically required in photo relay solutions.

The secondary side consists of back-to-back MOSFETs with a standoff voltage of ±1.2 kV from S1 to S2. The TPSI2140-Q1 MOSFET's avalanche robustness and thermally conscious package design allow it to robustly support system level dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without requiring any external components.

Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPSI2140-Q1 SOIC 11-pin (DWQ) 10.3 mm × 7.5 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20200615-SS0I-ZRWJ-LLQG-B43FBCBL3CCL-low.svg TPSI2140-Q1 Simplified Application Schematic