SBOSA18C may   2020  – june 2023 TSV911A-Q1 , TSV912A-Q1 , TSV914A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TSV911A-Q1
    5. 7.5 Thermal Information: TSV912A-Q1
    6. 7.6 Thermal Information: TSV914A-Q1
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input
      2. 8.3.2 Rail-to-Rail Output
      3. 8.3.3 Overload Recovery
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Input and ESD Protection
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Electrical Characteristics

VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOSInput offset voltageVS = 5 V±0.3±1.85mV
VS = 5 V
TA = –40°C to 125°C		±3
dVOS/dTDriftVS = 5 V
TA = –40°C to 125°C		±0.5µV/°C
PSRRPower-supply rejection ratioVS = 2.5 V – 5.5 V, VCM = (V–)±7µV/V
Channel separation, DCAt DC100dB
INPUT VOLTAGE RANGE
VCMCommon-mode voltage rangeVS = 2.5 V to 5.5 V(V–) – 0.1(V+) + 0.1V
CMRRCommon-mode rejection ratioVS = 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C		80103dB
VS = 5.5 V, VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C		5775
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C		88
VS = 2.5 V, VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C		70
INPUT BIAS CURRENT
IBInput bias current±5pA
IOSInput offset current±5pA
NOISE
EnInput voltage noise (peak-to-peak)VS = 5 V, f = 0.1 Hz to 10 Hz4.77µVPP
enInput voltage noise densityVS = 5 V, f = 10 kHz12nV/√ Hz
VS = 5 V, f = 1 kHz18
inInput current noise densityf = 1 kHz23fA/√ Hz
INPUT CAPACITANCE
CIDDifferential2pF
CICCommon-mode4pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gainVS = 2.5 V, (V–) + 0.04 V < VO < (V+) – 0.04 V
RL = 10 kΩ		100dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V
RL = 10 kΩ		104130
VS = 2.5 V, (V–) + 0.06 V < VO < (V+) – 0.06 V
RL = 2 kΩ		100
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V
RL = 2 kΩ		130
FREQUENCY RESPONSE
GBPGain bandwidth productVS = 5 V, G = 18MHz
φmPhase marginVS = 5 V, G = 155°
SRSlew rateVS = 5 V, G = 1
RL = 2 kΩ
CL = 100 pF		4.5V/µs
tSSettling timeTo 0.1%, VS = 5 V, 2-V step , G = 1
CL = 100 pF		0.5µs
To 0.01%, VS = 5 V, 2-V step , G = 1
CL = 100 pF		1
tOROverload recovery timeVS = 5 V, VIN  × gain > VS0.2µs
THD + NTotal harmonic distortion + noise(1)VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz0.0008%
OUTPUT
VOVoltage output swing from supply railsVS = 5.5 V, RL = 10 kΩ20mV
VS = 5.5 V, RL = 2 kΩ60
ISCShort-circuit currentVS = 5 V±50mA
ZOOpen-loop output impedanceVS = 5 V, f = 10 MHz100Ω
POWER SUPPLY
IQQuiescent current per amplifierVS = 5.5 V, IO = 0 mA550750µA
VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C1100
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.