SLLSF47D February   2018  – April 2024 TUSB1044

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.1
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Custom Alternate Mode
      5. 6.4.5 Linear EQ Configuration
      6. 6.4.6 Adjustable VOD Linear Range and DC Gain
      7. 6.4.7 USB3.1 Modes
    5. 6.5 Programming
      1. 6.5.1 Use The Following Procedure to Write to TUSB1044 I2C Registers:
      2. 6.5.2 Use The Following Procedure to Read the TUSB1044 I2C Registers:
      3. 6.5.3 Use The Following Procedure for Setting a Starting Sub-Address for I2C Reads:
    6. 6.6 Register Maps
      1. 6.6.1 TUSB1044 Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 System Examples
      1. 7.3.1 USB 3.1 only (USB/DP Alternate Mode)
      2. 7.3.2 USB3.1 and 2 lanes of DisplayPort
      3. 7.3.3 DisplayPort Only
      4. 7.3.4 USB 3.1 only (USB/Custom Alternate Mode)
      5. 7.3.5 USB3.1 and 1 Lane of Custom Alt Mode
      6. 7.3.6 USB3.1 and 2 Lane of Custom Alt Mode
      7. 7.3.7 USB3.1 and 4 Lane of Custom Alt Mode
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision C (October 2018) to Revision D (April 2024)

  • Changed condition for I2C VIH-3.3V From VIO_SEL = "0" or "R". To VIO_SEL = "0" or "F".Go
  • Changed condition for I2C VIL-3.3V From VIO_SEL = "0" or "R". To VIO_SEL = "0" or "F".Go
  • Changed condition for I2C VIH-1.8V From VIO_SEL = "F" or "1". To VIO_SEL = "R" or "1".Go
  • Changed condition for I2C VIL-1.8V From VIO_SEL = "F" or "1". To VIO_SEL = "R" or "1".Go
  • Changed dR maximum from 8.1 Gbps to 10.0 Gbps Go
  • Changed 8.1 Gbps to 10.0 GbpsGo
  • Changed DisplayPort 1.4 to DisplayPort 2.1Go
  • Changed HBR3 to UHBR10Go

Changes from Revision B (April 2018) to Revision C (October 2018)

  • Added pull-down indicator (PD) in the I/O column on SWAP, SLP_S0#, DIR0, DIR1, FLIP. CTL0 pins. Go
  • Added junction temperature of 105℃ for TUSB1044. Go
  • Changed junction temperature from 105℃ to 125℃ for TUSB1044I Go
  • Changed RPD_CTL1 From: Internal pull-down resistance for CTL1   To:  Internal pull-down resistance for CTL1, CTL0, DIR0, DIR1, FLIP, and SLP_S0#.Go
  • Added RPD_SWAP parameter of 200kΩ.Go

Changes from Revision A (February 2018) to Revision B (April 2018)

  • Changed the Simplified SchematicGo

Changes from Revision * (February 2018) to Revision A (February 2018)

  • Changed text in the Detailed Design Procedure From: "This AC-coupling capacitor should be no more than 220 nF." To: This AC-coupling capacitor should be no smaller than 297 nF. A value of 330 nF is recommended."Go
  • Changed 220 nF to 330 nF on DRX2P, DRX2N and DRX1P, DRX1N in Figure 7-2 Go