SCES641E May   2007  – October 2023 TXB0102

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: TA = 25°C
    6. 5.6  Electrical Characteristics: TA = –40°C to +85°C
    7. 5.7  Operating Characteristics
    8. 5.8  VCCA = 1.2 V Timing Requirements
    9. 5.9  VCCA = 1.5 V ± 0.1 V Timing Requirements
    10. 5.10 VCCA = 1.8 V ± 0.15 V Timing Requirements
    11. 5.11 VCCA = 2.5 V ± 0.2 V Timing Requirements
    12. 5.12 VCCA = 3.3 V ± 0.3 V Timing Requirements
    13. 5.13 VCCA = 1.2 V Switching Characteristics
    14. 5.14 VCCA = 1.5 V ± 0.1 V Switching Characteristics
    15. 5.15 VCCA = 1.8 V ± 0.15 V Switching Characteristics
    16. 5.16 VCCA = 2.5 V ± 0.2 V Switching Characteristics
    17. 5.17 VCCA = 3.3 V ± 0.3 V Switching Characteristics
    18. 5.18 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Architecture
      2. 7.3.2 Input Driver Requirements
      3. 7.3.3 Output Load Considerations
      4. 7.3.4 Enable and Disable
      5. 7.3.5 Pullup or Pulldown Resistors on I/O Lines
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Architecture

The TXB0102 architecture (see Figure 7-1) does not require a direction-control signal to control the direction of data flow from A to B or from B to A. In a DC state, the output drivers of the TXB0102 can maintain a high or low, but are designed to be weak, so that the drivers can be overdriven by an external driver when data on the bus starts flowing the opposite direction. The output one shots detect rising or falling edges on the A or B ports. During a rising edge, the one shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V and 40 Ω at VCCO = 3.3 V to 5 V.

GUID-927DC757-E45B-45C3-91A8-A6C8064B744F-low.gifFigure 7-1 Architecture of TXB0102 I/O Cell