SLUSF10B february   2023  – june 2023 UCC14141-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Insulation Specifications
    6. 7.6  Safety-Related Certifications
    7. 7.7  Electrical Characteristics
    8. 7.8  Safety Limiting Values
    9. 7.9  Insulation Characteristics
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Stage Operation
        1. 8.3.1.1 VDD-VEE Voltage Regulation
        2. 8.3.1.2 COM-VEE Voltage Regulation
        3. 8.3.1.3 Power Handling Capability
      2. 8.3.2 Output Voltage Soft Start
      3. 8.3.3 ENA and PG
      4. 8.3.4 Protection Functions
        1. 8.3.4.1 Input Undervoltage Lockout
        2. 8.3.4.2 Input Overvoltage Lockout
        3. 8.3.4.3 Output Undervoltage Protection
        4. 8.3.4.4 Output Overvoltage Protection
        5. 8.3.4.5 Overpower Protection
        6. 8.3.4.6 Overtemperature Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Capacitor Selection
        2. 9.2.2.2 Single RLIM Resistor Selection
        3. 9.2.2.3 RDR Circuit Component Selection
    3. 9.3 System Examples
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 ENA and PG

The ENA input pin and PG output pin on the primary-side use 5-V TTL and 3.3-V LVTTL level logic thresholds.

The active-high enable input (ENA) pin is used to turn-on the isolated DC/DC converter of the module. Either 3.3-V or 5-V logic rails can be used. Maintain the ENA pin voltage below 5.5 V. After ENA pin voltage becomes above the enable threshold VEN_IR, UCC14141-Q1 enables, starts switching, goes through the soft-start process and delivers power to the secondary side. After ENA pin voltage falls below the disable threshold VEN_IF, UCC14141-Q1 disables, stops switching.

The ENA pin can also be used to reset the UCC14141-Q1 device after it enters the protection safe-state mode. After a detected fault, the protection logic will latch off and place the device into a safe state. When all the faults are cleared, the ENA-pin can be used to clear the UCC14141-Q1 latch by toggling the ENA pin voltage below VEN_IF for longer than 150 μs, then toggling back up to 3.3 V or 5 V. The device will then exit the latch-off mode and we initiate a soft-start. Figure 8-6 illustrates the latch-off reset timing.

GUID-4A4EB226-305D-49D4-AA56-DCAEBBD3D8AB-low.svg Figure 8-6 Latch-off Reset Using ENA Pin

The active-low power-good (PG) pin is an open-drain output that indicates (short) when the module has no fault and the output voltages are within ±10% of the output voltage regulation setpoints. Connect a pull-up resistor (> 1 kΩ) from PG pin to either a 5-V or 3.3-V logic rail. Maintain the PG pin voltage below 5.5 V without exceeding its recommended operating voltage. The logic of PG pin can be illustrated using Figure 8-7.

GUID-2784548C-EA45-4ADD-A437-5B8FC5724361-low.svg Figure 8-7 PG Pin Logic