SLUSFA6 October   2023 UCC44273

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Low Propagation Delays
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Threshold Type
        2. 8.2.2.2 VDD Bias Supply Voltage
        3. 8.2.2.3 Peak Source and Sink Currents
        4. 8.2.2.4 Propagation Delay
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
      4. 8.4.4 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
BIAS CURRENTS
IDD(off) Startup current VDD = 3.4 V IN = VDD 40 100 160 µA
IN = GND 20 60 115
UNDER VOLTAGE LOCKOUT (UVLO)
VON Supply start threshold TA = 25°C 3.91 4.20 4.5 V
TA = -40°C to 140°C 3.70 4.20 4.65
VOFF Minimum operating voltage after supply start 3.45 3.9 4.35 V
VDD_H Supply voltage hysteresis 0.2 0.3 0.5 V
INPUTS (IN)
VIN_H Input signal high threshold Output high for IN pin 2.2 2.4 V
VIN_L Input signal low threshold Output low for IN pin 1.0 1.2 V
VIN_HYS Input signal hysteresis 1.0 V
SOURCE/SINK CURRENT
ISRC/SNK Source/sink peak current CLOAD = 0.22 µF, FSW = 1 kHz ±4 A
OUTPUTS (OUT)
VDD-VOH High output voltage VDD = 12 V
IOUT = -10 mA		 50 90 mV
VDD = 4.5 V
IOUT = -10 mA		 60 130
VOL Low output voltage VDD = 12
IOUT = 10 mA		 5 10 mV
VDD = 4.5 V
IOUT = 10 mA		 6 12
ROH Output pullup resistance(1) VDD = 12 V
IOUT = -10 mA		 5.0 7.5 Ω
VDD = 4.5 V
IOUT = -10 mA		 5.0 11.0
ROL Output pulldown resistance VDD = 12 V
IOUT = 10 mA		 0.5 1.0 Ω
VDD = 4.5 V
IOUT = 10 mA		 0.6 1.2
(1) ROH represents on-resistance of P-Channel MOSFET in pull-up structure of the UCC44273's output stage.