SLUS652E March   2005  – April 2020 UCD8220

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 UCD8220 Typical Simplified Push-Pull Converter Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CLK Input Time-Domain Digital Pulse Train
      2. 7.3.2 Current Sensing and Protection
      3. 7.3.3 Handshaking
      4. 7.3.4 Driver Output
      5. 7.3.5 Source and Sink Capabilities During Miller Plateau
      6. 7.3.6 Drive Current and Power Requirements
      7. 7.3.7 Clearing the Current-Limit Flag (CLF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control
        2. 8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward
        3. 8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VDD = 12 V, 4.7-µF capacitor from VDD to AGND, 1 μF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND, TA = TJ = –40°C to 105°C, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY SECTION
Supply current, OFF VDD = 4.2 V 300 500 µA
Supply current, ON Outputs not switching, CLK = low 2 3 mA
LOW VOLTAGE UNDERVOLTAGE LOCKOUT
VDD UVLO ON 4.25 4.5 4.75 V
VDD UVLO OFF 4.05 4.25 4.45 V
VDD UVLO hysteresis 150 250 350 mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point TA = 25°C, ILOAD = 0 3.267 3.3 3.333 V
3V3 set point over temperature 3.234 3.3 3.366 V
3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5 V 1 6.6 mV
3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 1 6.6 mV
Short circuit current VDD = 4.75 to 12 V 11 20 35 mA
3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 V
3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9 V
CLOCK INPUT (CLK)
VIT+ HIGH, positive-going input threshold voltage 1.65 2.08 V
VIT– LOW negative-going input threshold voltage 1.16 1.5 V
(VIT+) – (VIT–) Input voltage hysteresis 0.6 0.8 V
Frequency OUTx = 1 MHz 2 MHz
SLOPE COMPENSATION (ISET)
ISET Voltage VISET , 3V3 = 3.3 V, ±2% 1.78 1.84 1.90 V
m VSLOPE (I-Mode) RISET = 6.19 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V 1.48 2.12 2.76 V/µs
RISET = 100 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V 0.099 0.142 0.185
RISET = 499 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V 0.019 0.028 0.037
m VSLOPE (V-Mode) RISET = 4.99 kΩ to 3V3, CTRL = 2.5 V 1.44 2.06 2.68 V/µs
RISET = 100 kΩ to 3V3, CTRL = 2.5 V 0.079 0.114 0.148
RISET = 402 kΩ to 3v3, CTRL = 2.5 V 0.019 0.027 0.035
ISET resistor range Current mode control; RISET connected to AGND 6.19 499 kΩ
ISET resistor range Voltage mode control; RISET connected to 3V3 4.99 402 kΩ
ISET current range Voltage mode control with Feed-Forward; RISET connected to VIN 3.7 300 μA
PWM
PWM offset at CTRL input 3V3 = 3.3 V ±2% 0.45 0.51 0.6 V
CTRL buffer gain(1) Gain from CTRL to PWM comparator input 0.5 V/V
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold ILIM = OPEN 0.466 0.5 0.536 V
ILIM maximum current limit threshold ILIM = 3.3 V 0.975 1.025 1.075 V
ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 V
ILIM minimum current limit threshold ILIM = 0.25 V 0.2 0.23 0.25 V
CLF output high level CS > ILIM , ILOAD = –7 mA 2.64 V
CLF output low level CS ≤ ILIM, ILOAD = 7 mA 0.66 V
CURRENT SENSE COMPARATOR
Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current –1 μA
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance CLK = low, resistance from CS to AGND 10 35 75 Ω
OUTPUT DRIVERS
Source current(1) VDD = 12 V, CLK = high, OUTx = 5 V 4 A
Sink current(1) VDD = 12 V, CLK = low, OUTx = 5 V 4 A
Source current(1) VDD = 4.75 V, CLK = high, OUTx = 0 2 A
Sink current(1) VDD = 4.75 V, CLK = low, OUTx = 4.75 V 3 A
Output with VDD < UVLO VDD = 1.0 V, ISINK = 10 mA 0.8 1.2 V
(1) Specified by design. Not 100% tested in production.