JAJSN15 December   2023 ADS9227

ADVMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: ADS9228
    10. 5.10 Typical Characteristics: ADS9227
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Data Averaging
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Frame Width
        2. 6.3.6.2 Test Patterns for Data Interface
          1. 6.3.6.2.1 User-defined Test Pattern
          2. 6.3.6.2.2 User-defined Alternating Test Pattern
          3. 6.3.6.2.3 Ramp Test Pattern
      7. 6.3.7 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Timing Requirements

at AVDD_5V = 4.75 V to 5.25 V for ADS9228 and ADS9229, AVDD_5V = 4.5 V to 5.5 V for ADS9227 VDD_1V8 = 1.75 V to 1.85 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to 125°C; typical values at TA = 25°C.
MIN MAX UNIT
CONVERSION CYCLE
fCYCLE Sampling-frequency ADS9228 3.6 10 MHz
ADS9227 3.6 5
tCYCLE ADC cycle-time period 1 / fCYCLE s
tPL_SMPLCLK Sample clock low time 0.48 0.52 tCYCLE
tPH_SMPLCLK Sample clock high time 0.48 0.52 tCYCLE
fCLK Maximum SCLK frequency 10 MHz
tCLK Minimum SCLK time period 100 ns
SPI TIMINGS
thi_CSZ Pulse duration: CS high 220 ns
tPH_CK SCLK high time 0.48 0.52 tCLK
tPL_CK SCLK low time 0.48 0.52 tCLK
td_CSCK Setup time: CS falling to the first SCLK rising edge 20 ns
tsu_CKDI Setup time: SDI data valid to the corresponding SCLK rising edge 10 ns
tht_CKDI Hold time: SCLK rising edge to corresponding data valid on SDI 5 ns
td_CKCS Delay time: last SCLK falling edge to CS rising 5 ns