JAJSN15 December   2023 ADS9227

ADVMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: ADS9228
    10. 5.10 Typical Characteristics: ADS9227
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Data Averaging
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Frame Width
        2. 6.3.6.2 Test Patterns for Data Interface
          1. 6.3.6.2.1 User-defined Test Pattern
          2. 6.3.6.2.2 User-defined Alternating Test Pattern
          3. 6.3.6.2.3 Ramp Test Pattern
      7. 6.3.7 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

at AVDD_5V = 4.75 V to 5.25 V for ADS9228 and ADS9229, AVDD_5V = 4.5 V to 5.5 V for ADS9227 VDD_1V8 = 1.75 V to 1.85 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to 125°C; typical values at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IB Input bias current 0.5 TBD µA
Input bias current thermal drift 1 nA/℃
DC PERFORMANCE
Resolution No missing codes 16 Bits
DNL Differential nonlinearity –0.5 ±0.3 0.5 LSB
INL Integral nonlinearity –0.75 ±0.3 0.75 LSB
V(OS) Input offset error ±2 TBD LSB
dVOS/dT Input offset error thermal drift ±0.3 TBD ppm/°C
GE Gain error(1) –0.05 ±0.01 0.05 %FSR
dGE/dT Gain error thermal drift ±0.5 TBD ppm/°C
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio fIN = 2 kHz TBD 93.4 dB
fIN = 1 MHz 90.4
SNR Signal-to-noise ratio fIN = 2 kHz TBD 93.5 dBFS
fIN = 1 MHz 90.5
THD Total harmonic distortion fIN = 2 kHz –120 dB
fIN = 1 MHz –104
SFDR Spurious-free dynamic range fIN = 2 kHz 120 dB
fIN = 1 MHz 104
Isolation crosstalk fIN = 2 kHz TBD dB
SAMPLING DYNAMICS
BW Input-bandwidth ADS9228 90 MHz
ADS9227 45
COMMON-MODE OUTPUT BUFFER
VCMOUT Common-mode output voltage 2.4 V
Output current drive 0 5 μA
LVDS RECEIVER (SMPL_CLK)
VTH High-level input voltage 100 mV
VTL Low-level input voltage –100 mV
VICM Input common-mode voltage 0.3 1.2 1.4 V
LVDS OUTPUT (CLKOUT, DOUTA, and DOUTB)
VODIFF Differential output voltage RL = 100 Ω 250 350 450 mV
VOCM Output common-mode voltage RL = 100 Ω 1.08 1.1 1.32 V
CMOS INPUTS (CS, SCLK, and SDI)
VIL Input low logic level –0.1 0.5 V
VIH Input high logic level 1.3 VDD_1V8 V
CMOS OUTPUT (SDO)
VOL Output low logic level IOL = 200-µA sink 0 0.4 V
VOH Output high logic level IOH = 200-µA source 1.4 VDD_1V8 V
POWER SUPPLY
IAVDD_5V Supply current from AVDD_5V At 10 MSPS throughput (ADS9228) 30 40 mA
At 5 MSPS throughput (ADS9227) 18 24
Power-down 2
IVDD_1V8 Supply current from VDD_1V8 At 10 MSPS throughput (ADS9228) 68 89 mA
At 5 MSPS throughput (ADS9227) 51 66
Power-down 2
(1) These specifications include full temperature range variation but not the error contribution from internal reference.