JAJSGQ2F August 2013 – March 2019
PRODUCTION DATA.
The high efficiency of the bq25505 charger is achieved through the proprietary Nano-Power management circuitry and algorithm. This feature essentially samples and holds the VSTOR voltage to reduce the average quiescent current. That is, the internal circuitry is only active for a short period of time and then off for the remaining period of time at the lowest feasible duty cycle. A portion of this feature can be observed in Figure 20 where the VRDIV node is monitored. Here the VRDIV node provides a connection to the VSTOR voltage (first pulse) and then generates the reference levels for the VBAT_OV and VBAT_OK resistor dividers for a short period of time. The divided down values at each pin are compared against VBIAS as part of the hysteretic control. Because this biases a resistor string, the current through these resistors is only active when the Nano-Power management circuitry makes the connection—hence reducing the overall quiescent current due to the resistors. This process repeats every 64 ms.
The efficiency of the bq25505 boost charger is shown for various input power levels in Figure 1 through Figure 7. All data points were captured by averaging the overall input current. This must be done due to the periodic biasing scheme implemented via the Nano-Power management circuitry. In order to properly measure the resulting input current when calculating the output to input efficiency, the input current efficiency data was gathered using a source meter set to average over at least 50 samples. Quiescent currents into VSTOR, VBAT_SEC and VBAT_PRI over temperature and voltage are shown at Figure 8 through Figure 10.