JAJSU42A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RSN|32
サーマルパッド・メカニカル・データ
発注情報

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
DESCRIPTION PINS MIN MAX UNIT
Supply voltage range BAT VSS–0.3 VSS+60 V
Input voltage range, VIN PACK, LD VSS–0.3 VSS+60 V
Input voltage range, VIN PACK, PCHG, PDSG, LD the maximum of VBAT–10 or VLD–10  VSS+60 V
Input voltage range, VIN REGIN the maximum of VSS–0.3 or VBREG–5.5 the minimum of VSS+6 or VBAT+0.3 or VBREG+0.3 V
Input voltage range, VIN FUSE(2) VSS–0.3 the minimum of VSS+20 or VBAT+0.3 V
Input voltage range, VIN BREG the maximum of VSS–0.3 or VREGIN–0.3 VREGIN+5.5 V
Input voltage range, VIN REG1 VSS–0.3 minimum of VSS+6 or VREGIN+0.3 V
Input voltage range, VIN ALERT, SCL, SDA, CFETOFF, DFETOFF, RST_SHUT (3) VSS–0.3 VSS+6 V
Input voltage range, VIN TS1, TS2, ALERT, CFETOFF, DFETOFF, (when used as thermistor or general purpose ADC input) VSS–0.3 VREG18 + 0.3 V
Input voltage range, VIN SRP, SRN VSS–0.3 VREG18 + 0.3 V
Input voltage range, VIN VC5 maximum of VSS–0.3 and VC4A–0.3 VSS+60 V
Input voltage range, VIN VC4A maximum of VSS–0.3 and VC4B–0.3 VSS+60 V
Input voltage range, VIN VC4B maximum of VSS–0.3 and VC3A–0.3 VSS+60 V
Input voltage range, VIN VC3A maximum of VSS–0.3 and VC3B–0.3 VSS+60 V
Input voltage range, VIN VC3B maximum of VSS–0.3 and VC2–0.3 VSS+60 V
Input voltage range, VIN VC2 maximum of VSS–0.3 and VC1–0.3 VSS+60 V
Input voltage range, VIN VC1 maximum of VSS–0.3 and VC0–0.3 VSS+60 V
Input voltage range, VIN VC0 VSS–0.3 VSS+6 V
Output voltage range, VO CP1 VBAT–0.3 the minimum of VSS+60 or VBAT+15 V
Output voltage range, VO CHG VSS–0.3 VSS+60 V
Output voltage range, VO DSG VSS–0.3 VSS+60 V
Output voltage range, VO REG1, TS2 (for wakeup function), ALERT, CFETOFF, DFETOFF, when configured to drive a digital output VSS–0.3 VSS+6 V
Output voltage range, VO REG18 VSS–0.3 VSS+2 V
Maximum cell balancing current through a single cell VC0 – VC5 100 mA
Maximum VSS current, ISS 75 mA
Functional temperature, TFUNC –40 85 °C
Junction temperature, TJ –55 150 °C
Storage temperature, TSTG –55 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The current allowed to flow into the FUSE pin must be limited (such as by using external series resistance) to 2 mA or less.
(3) When the ALERT, CFETOFF, or DFETOFF pins are selected for thermistor input or general purpose ADC–input, their voltage is limited to VREG18 + 0.3 V. These pins can accept up to 6 V when configured for other uses, such as a digital input.