JAJSNA9 March   2023 BQ77205

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Fault Detection
      2. 8.3.2 Open Wire Fault Detection
      3. 8.3.3 Oscillator Health Check
      4. 8.3.4 Sense Positive Input for Vx
      5. 8.3.5 Output Drive, OUT
      6. 8.3.6 The LATCH Function
      7. 8.3.7 Supply Input, VDD
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 FAULT Mode
      3. 8.4.3 Customer Test Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Cell Connection Sequence
    2. 9.2 Systems Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2 Systems Example

In this application example, the choice of a FUSE or FETs is required on the OUT pin — configured as an active high drive to 6-V outputs.

GUID-20211216-SS0I-PFQ3-JQJZ-J3BN0QH7D9WN-low.gif Figure 9-3 5-Series Cell Configuration with Active High 6-V Option