JAJSNA9 March   2023 BQ77205

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Characteristics
    6. 7.6 Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Fault Detection
      2. 8.3.2 Open Wire Fault Detection
      3. 8.3.3 Oscillator Health Check
      4. 8.3.4 Sense Positive Input for Vx
      5. 8.3.5 Output Drive, OUT
      6. 8.3.6 The LATCH Function
      7. 8.3.7 Supply Input, VDD
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 FAULT Mode
      3. 8.4.3 Customer Test Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Cell Connection Sequence
    2. 9.2 Systems Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 DC Characteristics

Typical values stated where TA = 25°C and VDD = 18 V, MIN/MAX values stated where TA = –40°C to 85°C and VDD = 5 V to 27.5V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVER VOLTAGE PROTECTION (OV)
VOV OV Detection Range 3.55 5.1 V
VOV_STEP OV Detection Steps 25 mV
VOV_HYS OV Detection Hysteresis  Selected OV Hysterysis depends on part number. See device selection table for details. VOV – 50 mV
Selected OV Hysterysis depends on part number. See device selection table for details.  VOV – 100 mV
VOV_ACC OV Detection Accuracy TA = 25℃
 		 –10 10 mV
OV Detection Accuracy 0℃ ≤ TA ≤ 60℃
 		 –20 20 mV
OV Detection Accuracy -40℃ ≤ TA ≤ 110℃
 		 –50 50 mV
OPEN WIRE PROTECTION (OW)
VOW OW Detection Threshold Vn < Vn-1 where n = 2 to 5 –200 mV
V1 - VSS 500 mV
VOW_HYS OW Detection Hysteresis Vn < Vn-1 where n = 1 to 5 VOW +100 mV
VOW_ACC OW Detection Accuracy -40 ℃ ≤ TA ≤ 110℃ –25 25 mV
SUPPLY AND LEAKAGE CURRENT
ICC Supply Current No fault detected. 2 2.5 µA
IIN(1) Input Current at Vx Pins Vn - Vn-1 and V1 - VSS = 4V, where n = 2 to 5, Open Wire Enabled  –0.3 0.3 µA
Vn - Vn-1 and V1 - VSS = 4V, where n = 2 to 5, Open Wire Disabled  –0.1 0.1 µA
OUTPUT DRIVE, OUT pin, CMOS ACTIVE HIGH VERSIONS ONLY
VOUT_AH Output Drive Voltage for OUT, Active High 6V Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 5, VDD = 18V, IOH = 100 µA measured out of OUT pin. 6 V
Output Drive Voltage for OUT, Active High VDD VDD - VOUT , Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 5, IOH = 10 µA measured out of OUT pin. 0 1 1.5 V
Output Drive Voltage for DOUT, Active High 6V VDD - VOUT , If 4 of 5 cells are short circuited and only one cell remains powered and > VOV, VDD = Vx (cell voltage), IOH = 100 µA, 0 1 1.5 V
Output Drive Voltage for OUT, Active High 6V and VDD Vn - Vn-1 and V1 - VSS < VOV, where n = 2 to 5, VDD = 18 V, IOH = 100 µA measured into pin 250 400 mV
ROUT_AH Internal Pull Up Resistor 80 100 120 kΩ
IOUT_AH_H OUT Source Current (during OV) Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 5, VDD = 18 V, OUT = 0V. Measured out of OUT pin 6.5 mA
IOUT_AH_L OUT Sink Current (no OV) Vn - Vn-1 and V1 - VSS < VOV, where n = 2 to 5, VDD = 18 V, OUT = VDD. Measured into OUT pin 0.3 3 mA
OUTPUT DRIVE, OUT pin, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
VOUT_AL Output Drive Voltage for OUT, Active Low Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 5, VDD = 18 V, IOH = 100 µA measured into OUT pin. 250 400 mV
IOUT_AL_L OUT Source Current (during OV) Vn - Vn-1 or V1 - VSS > VOV, where n = 2 to 5, VDD = 18 V, OUT = VDD. Measured into OUT pin. 0.3 3 mA
IOUT_AL_H OUT Sink Current (no OV) Vn - Vn-1 and V1 - VSS < VOV, where n = 2 to 5, VDD = 18 V, OUT = VDD. Measured out of OUT pin. 100 nA
(1) Assured by Design.