JAJSSH0 December   2023 BQ77307

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ77307
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Current Detector
    10. 6.10 Thermistor Pullup Resistor
    11. 6.11 Hardware Overtemperature Detector
    12. 6.12 Internal Oscillator
    13. 6.13 Charge and Discharge FET Drivers
    14. 6.14 Protection Subsystem
    15. 6.15 Timing Requirements - I2C Interface, 100kHz Mode
    16. 6.16 Timing Requirements - I2C Interface, 400kHz Mode
    17. 6.17 Timing Diagram
    18. 6.18 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage Protection Subsystem
      2. 7.4.2  Current Protection Subsystem
      3. 7.4.3  Unused VC Pins
      4. 7.4.4  Internal Temperature Protection
      5. 7.4.5  Thermistor Temperature Protections
      6. 7.4.6  Protection FET Drivers
      7. 7.4.7  Voltage References
      8. 7.4.8  Multiplexer
      9. 7.4.9  LDOs
      10. 7.4.10 Standalone Versus Host Interface
      11. 7.4.11 ALERT Pin Operation
      12. 7.4.12 Low Frequency Oscillator
      13. 7.4.13 I2C Serial Communications Interface
    5. 7.5 Protection Subsystem
      1. 7.5.1 Protections Overview
      2. 7.5.2 Primary Protections
      3. 7.5.3 Cell Open Wire Protection
      4. 7.5.4 Diagnostic Checks
    6. 7.6 Device Power Modes
      1. 7.6.1 Overview of Power Modes
      2. 7.6.2 NORMAL Mode
      3. 7.6.3 SHUTDOWN Mode
      4. 7.6.4 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-3610B898-7815-4F0E-9D04-7ECFD25FE2BD-low.gifFigure 5-1 BQ77307 Pinout
Table 5-1 BQ77307 Pin Functions
PINI/OTYPEDESCRIPTION
NO.NAME
1VC4IIASense voltage input pin for the fourth cell from the bottom of the stack
2VC3IIASense voltage input pin for the third cell from the bottom of the stack
1VC2IIASense voltage input pin for the second cell from the bottom of the stack
2VC1IIASense voltage input pin for the first cell from the bottom of the stack
3VC0IIASense voltage input pin for negative terminal of the first cell from the bottom of stack and functions as wakeup from SHUTDOWN
6SRPIIAAnalog input pin connected to the internal current protection subsystem, which detects a voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
7SRNIIAAnalog input pin connected to the internal current protection subsystem, which detects a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
8TSI/OI/OAThermistor input and functions as wakeup from SHUTDOWN
9DSGOOANMOS Discharge FET drive output pin
10CHGOOANMOS Charge FET drive output pin
11VSS—PDevice ground
12SCLI/OI/ODI2C serial communication bus clock
13SDAI/OI/ODI2C serial communication bus data
14ALERTOODDigital interrupt output pin
15REGOUTOOALDO output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
16REGSRCIIAInput pin for REGOUT LDO also functions as a supply for the CHG and DSG FET drivers.
17BATIPPrimary power supply input pin
18VC7IIASense voltage input pin for the seventh cell from the bottom of the stack
19VC6IIASense voltage input pin for the sixth cell from the bottom of the stack
20VC5IIASense voltage input pin for the fifth cell from the bottom of the stack