SLLSEL1 November   2014 CDCL1810A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Tables
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for the SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
      2. 9.3.2 SDA/SCL Interface
        1. 9.3.2.1 SDA/SCL Bus Slave Device Address
        2. 9.3.2.2 SDA/SCL Connections Recommendations
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SDA/SCL Interface
      2. 9.5.2 Command Code Definition
      3. 9.5.3 SDA/SCL Timing Characteristics
      4. 9.5.4 SDA/SCL Programming Sequence
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Bus Configuration Command Bitmap
        1. 9.6.1.1 Byte 0:
        2. 9.6.1.2 Byte 1:
        3. 9.6.1.3 Byte 2:
        4. 9.6.1.4 Byte 3:
        5. 9.6.1.5 Byte 4:
        6. 9.6.1.6 Byte 5:
        7. 9.6.1.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  15. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Specifications

8.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
VDD, AVDD Supply voltage(2) –0.3 2.5 V
VLVDS Voltage range at LVDS input pins(2) –0.3 VDD+0.6 V
VI Voltage range at all non-LVDS input pins(2) –0.3 VDD+0.6 V
TJ Junction temperature +125 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

8.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 +150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 500
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VDD Digital supply voltage 1.7 1.8 1.9 V
AVDD Analog supply voltage 1.7 1.8 1.9 V
TA Ambient temperature (no airflow, no heatsink) –40 +85 °C
TJ Junction temperature +105 °C

8.4 Thermal Information

THERMAL METRIC(1) CDCL1810A UNIT
RGZ
48 PINS
RθJA Junction-to-ambient thermal resistance(2). 28.3, Airflow = 0 LFM °C/W
22.4, Airflow = 50 LFM
RθJC(top) Junction-to-case (top) thermal resistance 20.5
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board.

8.5 DC Electrical Characteristics

Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVDD Total current from digital 1.8V supply All outputs enabled; VDD = VDD,typ
650MHz LVDS input		 212 mA
IAVDD Total current from analog 1.8V supply All outputs enabled; AVDD = VDD,typ
650MHz LVDS input		 16 mA
VIL,CMOS Low level CMOS input voltage VDD = 1.8V –0.2 0.6 V
VIH,CMOS High level CMOS input voltage VDD = 1.8V VDD –0.6 VDD V
IIL,CMOS Low level CMOS input current VDD = VDD,max, VIL = 0.0V –120 μA
IIH,CMOS High level CMOS input current VDD = VDD,max, VIH = 1.9V 65 μA
VOL,SDA Low level CMOS output voltage for the SDA pin Sink current = 3 mA 0 0.2VDD V
IOL,CMOS Low level CMOS output current 8 mA

8.6 AC Electrical Characteristics

Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ZD,IN Differential input impedance for the LVDS input terminals 90 132 Ω
VCM,IN Common-mode voltage, LVDS input 1125 1200 1375 mV
VS,IN Single-ended LVDS input voltage swing 100 600 mVPP
VD,IN Differential LVDS input voltage swing 200 1200
tR,OUT,
tF,OUT		 Output signal rise/fall time 20%–80% 100 ps
VCM,OUT Common-mode voltage, CML outputs VDD – 0.31 VDD – 0.23 VDD – 0.19 V
VS,OUT Single-ended CML output voltage swing ac-coupled 180 230 280 mVPP
VD,OUT Differential CML output voltage swing measured in a 50-Ω scope; The CML output incorporates 50-Ω resistors to VDD 360 460 560
FIN Clock input frequency 650 MHz
FOUT Clock output frequency 650
ADDITIVE CLOCK OUTPUT JITTER
JOUT FIN = 30.72MHz, FOUT = 30.72MHz
VD,IN = 200mVPP		 10 Hz to 1 MHz offset 180 fs RMS
1 MHz to 5 MHz offset 348
12 kHz to 5 MHz offset 388
FIN = 30.72MHz, FOUT = 30.72MHz
VD,IN = 1200mVPP		 10 Hz to 1 MHz offset 175 fs RMS
1 MHz to 5 MHz offset 347
12 kHz to 5 MHz offset 388
FIN = 650MHz, FOUT = 650MHz
VD,IN = 200mVPP		 10 Hz to 1 MHz offset 41 fs RMS
1 MHz to 20 MHz offset 36
12 kHz to 20 MHz offset 42
FIN = 650MHz, FOUT = 650MHz
VD,IN = 1200mVPP		 10 Hz to 1 MHz offset 48 fs RMS
1 MHz to 20 MHz offset 33
12 kHz to 20 MHz offset 39
TP Input-to-output delay FIN = 30.72MHz,
FOUT = 30.72MHz
YP[9:0] outputs		 0.7 ns
TSOUT Clock output skew FIN = 30.72MHz,
FOUT = 30.72MHz
YP[9:0] outputs relative to YP[0]		 –64 64 ps

8.7 AC Electrical Characteristics for the SDA/SCL Interface(1)

PARAMETER MIN TYP MAX UNIT
fSCL SCL frequency 400 kHz
th(START) START hold time 0.6 μs
tw(SCLL) SCL low-pulse duration 1.3 μs
tw(SCLH) SCL high-pulse duration 0.6 μs
tsu(START) START setup time 0.6 μs
th(SDATA) SDA hold time 0 μs
tsu(DATA) SDA setup time 0.6 μs
tr(SDATA) SCL / SDA input rise time 0.3 μs
tf(SDATA) SCL / SDA input fall time 0.3 μs
tsu(STOP) STOP setup time 0.6 μs
tBUS bus free time 1.3 μs
(1) See Figure 7 for the timing behavior.

8.8 Typical Characteristics

Typical operating conditions are at VDD = 1.8V and TA = +25°C, VD,IN = 200mVPP (unless otherwise noted).
diff_op_v_lls781.gif
A.
Figure 1. Transient Performance:
FIN = 30.72 MHz, FOUT = 30.72 MHz
diff2_op_v_lls781.gif
Figure 2. Transient Performance:
FIN = 650 MHz, FOUT = 650 MHz