JAJSLU6B May 2023 – March 2024 DAC39RF10 , DAC39RFS10
PRODUCTION DATA
The device includes a crossbar immediately after coming out of the PHY that allows mapping of signals between lanes to simplify PCB routing between the Tx and Rx which could save PCB complexity or shorten the traces (reduce loss). See LANE_SELn.
The physical layer lanes (0SRX± to 15SRX±) must be routed to the appropriate JESD204C lanes (JESD0 to JESD15) based on the lanes defined in the bit packing diagrams shown in JESD204C Format Diagrams.