JAJSFF5F September   2007  – October 2018 DAC5652A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     機能ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC
    6. 6.6  Electrical Characteristics: AC
    7. 6.7  Electrical Characteristics: Digital Input
    8. 6.8  Electrical Characteristics: Power Supply
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Inputs
      2. 7.3.2 References
        1. 7.3.2.1 Internal Reference
        2. 7.3.2.2 External Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Interfaces
        1. 7.4.1.1 Dual-Bus Data Interface and Timing
        2. 7.4.1.2 Single-Bus Interleaved Data Interface and Timing
      2. 7.4.2 Gain Setting Option
      3. 7.4.3 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DAC Transfer Function
        1. 8.1.1.1 Analog Outputs
      2. 8.1.2 Output Configurations
      3. 8.1.3 Differential With Transformer
      4. 8.1.4 Single-Ended Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.1.1 Dual-Bus Data Interface and Timing

In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5652A consist of two independent, 10-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the CLKA/B lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRTA/B line.

The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock domains having equal periods (but possibly different phases) are input to the DAC5652A. This is defined by a minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs. This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.

DAC5652A TimingDual_las452.gifFigure 15. Dual-Bus Mode Operation