SGLS387H July   2007  – August 2016 DAC5675A-SP

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics (Unchanged After 100 kRad)
    6. 7.6 AC Electrical Characteristics (Unchanged After 100 kRad)
    7. 7.7 Digital Specifications (Unchanged After 100 kRad)
    8. 7.8 Electrical Characteristics
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 Clock Input
      3. 8.3.3 Supply Inputs
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Definitions of Specifications and Terminology
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

11 Layout

11.1 Layout Guidelines

  • DAC output termination should be placed as close as possible to outputs.
  • Keep routing for RBIAS short.
  • Decoupling capacitors should be placed as close as possible to supply pins.
  • Digital differential inputs must be 50 Ω to ground loosely coupled, or 100-Ω differential tightly coupled.
  • Digital differential inputs must be length matched.

11.2 Layout Example

DAC5675A-SP layout_top_LGS387.png Figure 26. Top Layer
DAC5675A-SP layout_bot_LGS387.png Figure 27. Bottom Layer

11.3 Thermal Considerations

This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly under the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends an 11.9-mm 2-board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically ground potential.

DAC5675A-SP estdevlife_gls387.gif Figure 28. Estimated Device Life at Elevated Temperatures Electromigration Fail Modes