DLPS206 May   2021 DLPC7540

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 FPD-Link LVDS Electrical Characteristics
    11. 6.11 USB Electrical Characteristics
    12. 6.12 System Oscillator Timing Requirements
    13. 6.13 Power Supply and Reset Timing Requirements
    14. 6.14 DMD HSSI Timing Requirements
    15. 6.15 DMD Low-Speed LVDS Timing Requirements
    16. 6.16 V-by-One Interface General Timing Requirements
    17. 6.17 FPD-Link Interface General Timing Requirements
    18. 6.18 Source Frame Timing Requirements
    19. 6.19 Synchronous Serial Port Interface Timing Requirements
    20. 6.20 Master and Slave I2C Interface Timing Requirements
    21. 6.21 Programmable Output Clock Timing Requirements
    22. 6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    23. 6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    24. 6.24 Multi-Trace ETM Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 V-by-One interface
      5. 7.3.5 DMD (HSSI) Interface
      6. 7.3.6 Program Memory Flash Interface
      7. 7.3.7 GPIO Supported Functionality
      8. 7.3.8 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
        2. 7.4.2.2 Low Latency Configuration
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
    1. 9.1 Power Supply Management
    2. 9.2 Hot Plug Usage
    3. 9.3 Power Supplies for Unused Input Source Interfaces
    4. 9.4 Power Supplies
      1. 9.4.1 1.15-V Power Supplies
      2. 9.4.2 1.21V Power Supply
      3. 9.4.3 1.8-V Power Supplies
      4. 9.4.4 3.3-V Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Layout Guidelines
      2. 10.1.2  Power Supply Layout Guidelines
      3. 10.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 10.1.4  Layout Guideline for DLPC7540 Reference Clock
        1. 10.1.4.1 Recommended Crystal Oscillator Configuration
      5. 10.1.5  V-by-One Interface Layout Considerations
      6. 10.1.6  FPD-Link Interface Layout Considerations
      7. 10.1.7  USB Interface Layout Considerations
      8. 10.1.8  DMD Interface Layout Considerations
      9. 10.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Package Data
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
      1. 11.4.1 Video Timing Parameter Definitions
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

USB Interface Layout Considerations

The DLPC7540 USB differential interface waveform quality and timing is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

DLPC7540 I/O timing parameters, USB transmitter and receiver timing parameters, as well as USB specific timing requirements can be found in their corresponding data sheets. PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB related requirements for USB are provided in Table 10-7 as a starting point for the customer.

Table 10-7 USB Interface PBC Related Requirements (1)(2)
PARAMETERMINTYPMAXUNIT
Cross-talk between data lane (USB_DAT_P, USB_DAT_N) and other signals< 1.5mVpp
Intra-lane skew (USB_DAT_P, USB_DAT_N)< 20ps
Differential Impedance (USB_DAT_P, USB_DAT_N)76.590103.5Ω
Single Mode impedance (USB_DAT_P, USB_DAT_N)45Ω
Common Mode Impedance (USB_DAT_P, USB_DAT_N)213039Ω
Parasitic resistance (USB_DAT_P, USB_DAT_N)≤ 0.5Ω
Total capacitance (USB_DAT_P, USB_DAT_N)< 4pF
Differences of trace capacitance between USB_DAT_P, USB_DAT_N< 1pF
TXRTUNE resistor172.26174175.74Ω
If using the minimum trace width and spacing to escape the Controller ball field, widening these out after escape is desirable if practical to achieve the target 100 Ω impedance (e.g. to reduce transmission line losses).
One pcb layout example for the differential pair is shown in Figure 10-14

Additional layout guidelines for USB_DAT_P/USB_DAT_N:

  • Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the number of necessary vias to two.
  • Route differential signal pairs over a single ground or power plane using a Micro-strip line configuration. Ground guard traces are also recommended.
  • Do not route the differential signal pairs over the slit of power or ground planes.
  • Minimize the trace length mismatch for each pair, and between each pair, in order to meet the skew requirements.
  • Ensure that the bend angles associated with the differential signal pair are between 135o and 225o. (See Figure 10-15).
  • Minimize the length where the differential signal pair are parallel to clocks or digital signals.
  • Do not route the differential signal pair under an IC that uses a quartz crystal, oscillator, clock synchronization circuit, magnetic device, or clock.

GUID-720CCF29-4D1A-4CE1-BFE2-29BB681E2619-low.gifFigure 10-14 USB Layout Example
GUID-E70B5347-317D-41A8-813B-0E009B572158-low.gifFigure 10-15 USB Routing Example

Additional USB layout guidelines for TXRTUNE

  • Use the shortest possible connection lengths for the resistor between TXRTUNE and ground.
  • Use ground layer and ground guard traces to shield the wires and resistor.