8.6.68 DSP_CFG_27 Register (Offset = 0x33E) [reset = 0x261E]
DSP_CFG_27 is shown in Table 80.
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Table 80. DSP_CFG_27 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15 |
cfg_wait_lpi_el_dis |
R/W |
0x0 |
EEE_WAKE_CTRL register
|
14-13 |
cfg_dfe_coeff_lim_sel |
R/W |
0x1 |
Enable limit on the max limit of dfe coefficient
|
12-8 |
cfg_dfe_coeff_lim_val |
R/W |
0x6 |
Limit value for dfe coefficeint
|
7 |
cfg_wait_lpi_ed_dis |
|
0x0 |
EEE_WAKE_CTRL register
|
6 |
cfg_mse_th_scaled_en |
R/W |
0x0 |
Enable scaling of mse threshold based on PGA gain for DEQ sweep
|
5 |
cfg_dfe_th_scaled_en |
R/W |
0x0 |
Enable scaling of dfe threshold based on PGA gain for DEQ sweep
|
4-0 |
cfg_dfe_mse_th_offset |
R/W |
0x1E |
Offset to be added to PGA attenuation level used for scaling of mse and dfe thresholds
|