JAJSQT9A November   2023  – March 2024 DRV8242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN (20) package
    2. 5.2 SPI Variant
      1. 5.2.1 VQFN (20) package
      2. 5.2.2 VQFN (20) package
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information VQFN-RHL package
    5. 6.5  Electrical Characteristics
    6. 6.6  Transient Thermal Impedance & Current Capability
    7. 6.7  SPI Timing Requirements
    8. 6.8  Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
    9. 6.9  Wake-up Transients
      1. 6.9.1 HW Variant
      2. 6.9.2 SPI Variant
    10. 6.10 Fault Reaction Transients
      1. 6.10.1 Retry setting
      2. 6.10.2 Latch setting
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 PH/EN mode
        2. 7.3.2.2 PWM mode
        3. 7.3.2.3 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Power On Reset (POR)
        8. 7.3.4.8 Event Priority
    4. 7.4 Device Functional States
      1. 7.4.1 SLEEP State
      2. 7.4.2 STANDBY State
      3. 7.4.3 Wake-up to STANDBY State
      4. 7.4.4 ACTIVE State
      5. 7.4.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
    5. 7.5 Programming - SPI Variant Only
      1. 7.5.1 SPI Interface
      2. 7.5.2 Standard Frame
      3. 7.5.3 SPI Interface for Multiple Peripherals
        1. 7.5.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.1.1 VQFN (20) package

GUID-20220809-SS0I-GHLH-VF2J-JNNM4DLMS5MC-low.svg Figure 5-1 DRV8242H-Q1 HW variant in VQFN (20) package
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 SR I Device configuration pin for Slew Rate control . For details, refer to Section 7.3.3.1 in the Section 7.3.3.
2 DIAG I Device configuration pin for load type indication and fault reaction configuration. For details, refer to Section 7.3.3.4 in the Section 7.3.3.
3 PH/IN2 I Controller input pin for bridge operation. For details, see the Section 7.3.2.
4 EN/IN1 I Controller input pin for bridge operation. For details, see the Section 7.3.2.
5 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Section 7.3.2.
6, 15 VM P Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins (2 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic capacitor and a bulk capacitor.
7, 8 OUT1 P Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of OUT1 pins (2 total) to support device current capability.
9, 10, 11, 12 GND G Ground pin. Must combine with the rest of GND pins (4 total) to support device current capability.
13,14 OUT2 P Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of OUT2 pins (2 total) to support device current capability.
16 nSLEEP I Controller input pin for SLEEP. For details, see the Section 7.3.2.
17 IPROPI I/O Driver load current analog feedback. For details, refer to Section 7.3.3.2 in the Section 7.3.3.
18 nFAULT OD Fault indication to the controller. For details, refer to nFAULT in the Section 7.3.3.
19 MODE I Device configuration pin for MODE. For details, refer to the Section 7.3.3.
20 ITRIP I Device configuration pin for ITRIP level for high-side current limiting. For details, refer to ITRIP in the Section 7.3.3.
(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output