JAJSI55C November   2015  – October 2019 DS280BR810

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics -- Serial Management Bus Interface
    7. 6.7 Timing Requirements -- Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver and Transmitter
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連文書
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Requirements -- Serial Management Bus Interface

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SMBus SLAVE MODE)
fSDC SDC clock frequency EN_SMB = 1 k to VDD (Slave Mode) 10 100 400 kHz
TSDA-HD Data hold time 0.75 ns
TSDA-SU Data setup time 100 ns
TSDA-R SDA rise time, read operation Pull-up resistor = 1 kΩ, Cb = 50 pF 150 ns
TSDA-F SDA fall time, read operation Pull-up resistor = 1 kΩ, Cb = 50 pF 4.5 ns
SMBus SWITCHING CHARACTERISTICS (SMBus MASTER MODE)
fSDC SDC clock frequency EN_SMB = Float (Master Mode) 260 303 346 kHz
TSDC-LOW SDC low period 1.66 1.90 2.21 µs
TSDC-HIGH SDC high period 1.22 1.40 1.63 µs
THD-START Hold time start operation 0.6 µs
TSU-START Setup time start operation 0.6 µs
TSDA-HD Data hold time 0.9 µs
TSDA-SU Data setup time 0.1 µs
TSU-STOP Stop condition setup time 0.6 µs
TBUF Bus free time between Stop-Start 1.3 µs
TSDC-R SDC rise time Pull-up resistor = 1 kΩ 300 ns
TSDC-F SDFC fall time Pull-up resistor = 1 kΩ 300 ns