JAJSGT3B September   2005  – January 2019 DS90LT012AH

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      接続図
      2.      機能図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Termination
      2. 8.3.2 Threshold
      3. 8.3.3 Fail-Safe Feature
      4. 8.3.4 Probing LVDS Transmission Lines
      5. 8.3.5 Cables and Connectors, General Comments
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Point-to-Point Communications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Receiver Bypass Capacitance
          2. 9.2.1.2.2 Interconnecting Media
          3. 9.2.1.2.3 PCB Transmission Lines
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1)(2)
PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT
VTH Differential Input High Threshold VCM dependant on VDD(3) IN+, IN− −30 0 mV
VTL Differential Input Low Threshold −100 −30 mV
VCM Common-Mode Voltage VDD = 2.7 V, VID = 100 mV 0.05 2.35 V
VDD = 3 V to 3.6 V, VID = 100 mV 0.05 VDD – 0.3 V
TA = 125°C 0.1 2.35 V
IIN Input Current (DS90LV012A) VIN = +2.8 V VDD = 3.6 V or 0 V −10 ±1 +10 μA
VIN = 0 V −10 ±1 +10 μA
VIN = +3.6 V VDD = 0 V −20 +20 μA
ΔIIN Change in Magnitude of IIN VIN = +2.8 V VDD = 3.6 V or 0 V 4 μA
VIN = 0 V 4 μA
VIN = +3.6 V VDD = 0 V 4 μA
IIND Differential Input Current VIN+ = +0.4 V, VIN− = +0 V 3 3.9 4.4 mA
VIN+ = +2.4 V, VIN− = +2.0 V
RT Integrated Termination Resistor 100 Ω
CIN Input Capacitance IN+ = IN− = GND 3 pF
VOH Output High Voltage IOH = −0.4 mA, VID = +200 mV TTL OUT 2.4 3.1 V
IOH = −0.4 mA, Inputs terminated 2.4 3.1 V
IOH = −0.4 mA, Inputs shorted 2.4 3.1 V
VOL Output Low Voltage IOL = 2 mA, VID = −200 mV 0.3 0.5 V
IOS Output Short-Circuit Current VOUT = 0V (4) −15 −50 −100 mA
VCL Input Clamp Voltage ICL = −18 mA −1.5 −0.7 V
IDD No Load Supply Current Inputs Open VDD 5.4 9 mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID).
(2) All typicals are given for: VDD = +3.3 V and TA = +25°C.
(3) VDD is always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05 V to +2.35 V when VDD = 2.7 V and |VID| / 2 to VDD − 0.3 V when VDD = 3.0 V to 3.6 V. VID is not allowed to be greater than 100 mV when VCM = 0.05 V to 2.35 V when VDD = 2.7 V or when VCM = |VID| / 2 to VDD − 0.3 V when VDD = 3.0 V to 3.6 V.
(4) Output short-circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification.