JAJSGI8D April   2016  – October 2019 DS90UB914A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: DS90UB914A-Q1 Deserializer
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
    7. 8.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 8.8 Deserializer Switching Characteristics
    9. 8.9 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Timing Diagrams and Test Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Serial Frame Format
      2. 10.3.2  Line Rate Calculations for the DS90UB913A/914A
      3. 10.3.3  Deserializer Multiplexer Input
      4. 10.3.4  Error Detection
      5. 10.3.5  Synchronizing Multiple Cameras
      6. 10.3.6  General-Purpose I/O (GPIO) Descriptions
      7. 10.3.7  LVCMOS VDDIO Option
      8. 10.3.8  EMI Reduction
        1. 10.3.8.1 Deserializer Staggered Output
        2. 10.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
      9. 10.3.9  Pixel Clock Edge Select (TRFB / RRFB)
      10. 10.3.10 Power Down
    4. 10.4 Device Functional Modes
      1. 10.4.1 DS90UB913A/914A Operation With External Oscillator as Reference Clock
      2. 10.4.2 DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
      3. 10.4.3 MODE Pin on Deserializer
      4. 10.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      5. 10.4.5 Built-In Self Test
      6. 10.4.6 BIST Configuration and Status
      7. 10.4.7 Sample BIST Sequence
    5. 10.5 Programming
      1. 10.5.1 Programmable Controller
      2. 10.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 10.5.3 I2C Pass-Through
      4. 10.5.4 Slave Clock Stretching
      5. 10.5.5 ID[x] Address Decoder on the Deserializer
      6. 10.5.6 Multiple Device Addressing
    6. 10.6 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Power Over Coax
      2. 11.1.2 Power-Up Requirements and PDB Pin
      3. 11.1.3 AC Coupling
      4. 11.1.4 Transmission Media
      5. 11.1.5 Adaptive Equalizer – Loss Compensation
    2. 11.2 Typical Applications
      1. 11.2.1 Coax Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curves
      2. 11.2.2 STP Application
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Interconnect Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.4.3 MODE Pin on Deserializer

The MODE pin on the Deserializer can be used to configure the device to work in the 12-bit low-frequency mode, 12-bit high-frequency mode, or the 10-bit mode of operation. Internally, the DS90UB913A/914A chipset operates in a divide-by-1 mode in the 12-bit low-frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5 mode in the 12-bit high frequency mode. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and a pulldown resistor RMODE of the recommended value to set the different modes in the Deserializer as mentioned in Table 2. The Deserializer automatically configures the Serializer to correct mode via the back-channel. The recommended maximum resistor tolerance is 1%.

DS90UB914A-Q1 914A_mode.gifFigure 18. Mode Pin Configuration on DS90UB914A-Q1 Deserializer

Table 2. DS90UB914A-Q1 Deserializer MODE Resistor Value

DS90UB914A-Q1 DESERIALIZER MODE RESISTOR VALUE
MODE SELECT RMODE RESISTOR VALUE (kΩ)
12-bit low frequency mode 25-50 MHz PCLK, 10/12-bits DATA+ 2 SYNC.
Note: No HS/VS restrictions (raw).		 0
12-bit high frequency mode 37.5-75 MHz PCLK, 10/12-bits DATA+ 2 SYNC.
Note: No HS/VS restrictions (raw).		 3
10-bit mode 50–100 MHz PCLK, 10-bits DATA+ 2 SYNC.
Note: HS/VS restricted to no more than one transition per 10 PCLK cycles.		 11