SLLSEJ0H Data sheet

SLLSEJ0H October 2014 – March 2024 ISO7842

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

DWW|16
DW|16

サーマルパッド・メカニカル・データ

発注情報

5.16 Switching Characteristics—3.3V Supply

V_CC1 = V_CC2 = 3.3V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 6-1	6	10.8	16	ns
PWD	Pulse width distortion⁽¹⁾ \|t_PHL – t_PLH\|	See Figure 6-1		0.7	4.2	ns
t_sk(o)	Channel-to-channel output skew time⁽²⁾	Same-direction channels			2.2	ns
t_sk(pp)	Part-to-part skew time				4.5	ns
t_r	Output signal rise time	See Figure 6-1		0.8	3	ns
t_f	Output signal fall time	See Figure 6-1		0.8	3	ns
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 6-2		17	32	ns
t_PLZ	Disable propagation delay, low-to-high impedance output			17	32	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7842			17	32	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7842F			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7842			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7842F			17	32	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 6-3		0.2	9	μs
t_ie	Time interval error	2¹⁶ – 1 PRBS data at 100 Mbps		0.91		ns

(1) Also known as Pulse Skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.