SLLSEJ0H October   2014  – March 2024 ISO7842

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics–5V Supply
    10. 5.10 Supply Current Characteristics–5V Supply
    11. 5.11 Electrical Characteristics—3.3V Supply
    12. 5.12 Supply Current Characteristics—3.3V Supply
    13. 5.13 Electrical Characteristics—2.5V Supply
    14. 5.14 Supply Current Characteristics—2.5V Supply
    15. 5.15 Switching Characteristics—5V Supply
    16. 5.16 Switching Characteristics—3.3V Supply
    17. 5.17 Switching Characteristics—2.5V Supply
    18. 5.18 Insulation Characteristics Curves
    19. 5.19 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device I/O Schematics
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  10. 8 Power Supply Recommendations
  11. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PCB Material
    2. 9.2 Layout Example
  12. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  13. 11Revision History
  14. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • DWW|16
  • DW|16
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

PARAMETERTEST CONDITIONSSPECIFICATIONUNIT
DWDWW
GENERAL
CLRExternal clearance(1)Shortest pin-to-pin distance through air>8.15>14.5mm
CPGExternal creepage(1)Shortest pin-to-pin distance across the package surfaceHigh Voltage Feature Description>8.15>14.5mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>21>21μm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A>600>600V
Material groupII
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600 VRMSI–IVI–IV
Rated mains voltage ≤ 1000 VRMSI–IIII–IV
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORMMaximum repetitive peak isolation voltage21212828VPK
VIOWMMaximum isolation working voltageAC voltage (sine wave); Time dependent dielectric breakdown (TDDB) Test, see Figure 5-1 and Figure 5-215002000VRMS
DC voltage21212828VDC
VIOTMMaximum transient isolation voltageVTEST = 1.2 × VIOTM
t = 60 s (qualification)
t= 1 s (100% production)		80008000VPK
VIMP Maximum impulse voltage (3) Tested in air, 1.2/50-us waveform per IEC 62368-1 9800 9800 VPK
VIOSMMaximum surge isolation voltage (4)VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test), 1.2/50-μs waveform per IEC 62368-11280012800VPK
qpdApparent charge (5)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIOTM = 2545 VPK (DW) and 3394 VPK (DWW), tm = 10 s		≤5≤5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK (DWW), tm = 10 s		≤5≤5

Method b: At routine test (100% production);

Vini = 1.2 x VIOTM, tini = 1 s;

Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or

Vpd(m) = Vini, tm = tini (method b2)

≤5≤5
CIOBarrier capacitance, input to output(6)VIO = 0.4 × sin (2πft), f = 1 MHz22pF
RIOIsolation resistance, input to output (6)VIO = 500 V, TA = 25°C>1012>1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011>1011
VIO = 500 V at TS = 150°C>109>109
Pollution degree22
Climatic category55/125/2155/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production)		57005700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-pin device.