JAJSB70C July   2000  – October 2018 LF198-N , LF298 , LF398-N

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的な接続
      2.      アクイジション時間
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics, LF198-N and LF298
    5. 7.5 Electrical Characteristics, LF198A-N
    6. 7.6 Electrical Characteristics, LF398-N
    7. 7.7 Electrical Characteristics, LF398A-N (OBSOLETE)
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
    2. 8.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
    3. 8.3 Operational Amplifier Drive
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Hold Capacitor
      2. 10.1.2 DC and AC Zeroing
      3. 10.1.3 Logic Rise Time
      4. 10.1.4 Sampling Dynamic Signals
      5. 10.1.5 Digital Feedthrough
    2. 10.2 Typical Applications
      1. 10.2.1  X1000 Sample and Hold
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2  Sample and Difference Circuit
      3. 10.2.3  Ramp Generator With Variable Reset Level
      4. 10.2.4  Integrator With Programmable Reset Level
      5. 10.2.5  Output Holds at Average of Sampled Input
      6. 10.2.6  Increased Slew Current
      7. 10.2.7  Reset Stabilized Amplifier
      8. 10.2.8  Fast Acquisition, Low Droop Sample and Hold
      9. 10.2.9  Synchronous Correlator for Recovering Signals Below Noise Level
      10. 10.2.10 2-Channel Switch
      11. 10.2.11 DC and AC Zeroing
      12. 10.2.12 Staircase Generator
      13. 10.2.13 Differential Hold
      14. 10.2.14 Capacitor Hysteresis Compensation
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デバイスの項目表記
    2. 13.2 関連リンク
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage ±18 V
Power dissipation (Package limitation, see (3)) 500 mW
Operating ambient temperature LF198-N, LF198A-N –55 125 °C
LF298 –25 85 °C
LF398-N, LF398A-N 0 70 °C
Input voltage ±18 V
Logic-to-logic reference differential voltage (see (4)) 7 −30 V
Output short circuit duration Indefinite
Hold capacitor short circuit duration 10 sec
Lead temperature H package (soldering, 10 sec.) 260 °C
N package (soldering, 10 sec.) 260 °C
M package: vapor phase (60 sec.) 215 °C
Infrared (15 sec.) 220 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA) / RθJA, or the number given in the Absolute Maximum Ratings, whichever is lower. The maximum junction temperature, TJMAX, for the LF198-N and LF198A-N is 150°C; for the LF298, 115°C; and for the LF398-N and LF398A-N, 100°C.
(4) Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2 V below the positive supply and 3 V above the negative supply.