JAJSFB3 April   2018 LM25119Q

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-Up Regulator
      2. 8.3.2  UVLO
      3. 8.3.3  Enable 2
      4. 8.3.4  Oscillator and Sync Capability
      5. 8.3.5  Error Amplifiers and PWM Comparators
      6. 8.3.6  Ramp Generator
      7. 8.3.7  Current Limit
      8. 8.3.8  Hiccup Mode Current Limiting
      9. 8.3.9  Soft Start
      10. 8.3.10 HO and LO Output Drivers
      11. 8.3.11 Maximum Duty Cycle
      12. 8.3.12 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Diode Emulation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Miscellaneous Functions
      2. 9.1.2 Interleaved Two-Phase Operation
      3. 9.1.3 Interleaved 4-Phase Operation
    2. 9.2 Typical Applications
      1. 9.2.1 Dual-output Design Example
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 External Components
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Timing Resistor
          2. 9.2.1.2.2  Output Inductor
          3. 9.2.1.2.3  Current Sense Resistor
          4. 9.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 9.2.1.2.5  Output Capacitors
          6. 9.2.1.2.6  Input Capacitors
          7. 9.2.1.2.7  VCC Capacitor
          8. 9.2.1.2.8  Bootstrap Capacitor
          9. 9.2.1.2.9  Soft Start Capacitor
          10. 9.2.1.2.10 Restart Capacitor
          11. 9.2.1.2.11 Output Voltage Divider
          12. 9.2.1.2.12 UVLO Divider
          13. 9.2.1.2.13 MOSFET Selection
          14. 9.2.1.2.14 MOSFET Snubber
          15. 9.2.1.2.15 Error Amplifier Compensation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Two-Phase Design Example
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Switching Jitter Root Causes and Solutions
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 コミュニティ・リソース
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.2.13 MOSFET Selection

Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the losses in the high-side and low-side MOSFETs is one way to compare the relative efficiencies of different devices. When using discrete SO-8 MOSFETs, generally the output current capability range is 2 A to 10 A. Losses in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss. Conduction loss PDC is approximately Equation 36 and the example (Equation 37).

Equation 36. LM25119Q 30126260.gif
Equation 37. LM25119Q 30126261.gif

where

  • D is the duty cycle
  • The 1.3 factor accounts for the increase in MOSFET ON-resistance due to heating

Alternatively, the factor of 1.3 can be eliminated and the high temperature ON-resistance of the MOSFET can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet. Gate charging loss, PGC, results from the current driving the gate capacitance of the power MOSFETs and is approximated with Equation 38.

Equation 38. LM25119Q 30126262.gif

where

  • Qg refers to the total gate charge of an individual MOSFET
  • n is the number of MOSFETs

Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM25119Q device and not in the MOSFET itself. Further loss in the device is incurred if the gate driving current is supplied by the internal linear regulator.

Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the channel of the MOSFET. The switching loss can be approximated with Equation 39.

Equation 39. LM25119Q 30126263.gif

where

  • tR and tF are the rise and fall times of the MOSFET

The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the high-side MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-side MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turnon. For this example, the maximum drain-to-source voltage applied to either MOSFET is 36 V. The selected MOSFETs must be able to withstand 36 V plus any ringing from drain to source, and be able to handle at least the VCC voltage plus any ringing from gate to source. A good choice of MOSFET for the 36-V input design example is the SI7884. It has an RDS(ON) of 7.5 mΩ and total gate charge of 21 nC. In applications where a high step-down ratio is maintained in normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower Qg, and low-side MOSFET with lower RDS(ON).