JAJSF96C April   2018  – October 2021 LM5036

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Undervoltage Lockout (UVLO)
      3. 7.3.3  Reference Regulator
      4. 7.3.4  Oscillator, Synchronized Input
      5. 7.3.5  Voltage-Mode Control
      6. 7.3.6  Primary-Side Gate Driver Outputs (LSG and HSG)
      7. 7.3.7  Half-Bridge PWM Scheme
      8. 7.3.8  Maximum Duty Cycle Operation
      9. 7.3.9  Pre-Biased Start-Up Process
        1. 7.3.9.1 Primary FETs Soft-Start Process
        2. 7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
      10. 7.3.10 Zero Duty Cycle Operation
      11. 7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
      12. 7.3.12 Reverse Current Protection
      13. 7.3.13 CBC Threshold Accuracy
      14. 7.3.14 Hiccup Mode Protection
      15. 7.3.15 Hiccup Mode Blanking
      16. 7.3.16 Over-Temperature Protection (OTP)
      17. 7.3.17 Over-Voltage / Latch (ON_OFF Pin)
      18. 7.3.18 Auxiliary Constant On-Time Control
      19. 7.3.19 Auxiliary On-Time Generator
      20. 7.3.20 Auxiliary Supply Current Limiting
      21. 7.3.21 Auxiliary Primary Output Capacitor Ripple
      22. 7.3.22 Auxiliary Ripple Configuration and Control
      23. 7.3.23 Asynchronous Mode Operation of Auxiliary Supply
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Input Transient Protection
        3. 8.2.2.3  Level-Shift Detection Circuit
        4. 8.2.2.4  Applications with VIN > 100-V
        5. 8.2.2.5  Applications without Pre-Biased Start-Up Requirement
        6. 8.2.2.6  UVLO Voltage Divider Selection
        7. 8.2.2.7  Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
        8. 8.2.2.8  SS Capacitor
        9. 8.2.2.9  SSSR Capacitor
        10. 8.2.2.10 Half-Bridge Power Stage Design
        11. 8.2.2.11 Current Limit
        12. 8.2.2.12 Auxiliary Transformer
        13. 8.2.2.13 Auxiliary Feedback Resistors
        14. 8.2.2.14 RON Resistor
        15. 8.2.2.15 VIN Pin Capacitor
        16. 8.2.2.16 Auxiliary Primary Output Capacitor
        17. 8.2.2.17 Auxiliary Secondary Output Capacitor
        18. 8.2.2.18 Auxiliary Feedback Ripple Circuit
        19. 8.2.2.19 Auxiliary Secondary Diode
        20. 8.2.2.20 VCC Diode
        21. 8.2.2.21 Opto-Coupler Interface
        22. 8.2.2.22 Full-Bridge Converter Applications
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Auxiliary Ripple Configuration and Control

The voltage ripple across the output capacitor CAUX1 is made up of two components:

  • Resistive ripple appears across the equivalent series resistance (ESR) of the output capacitor. This component of ripple is in phase with the inductor current and is 90° delayed compared with the applied PWM signal.
  • Capacitive ripple appears across the ideal capacitor. This component of ripple is 90° delayed compared with the inductor current ripple and 180° delayed compared with the applied PWM signal.

With COT control, the on-time of the high-side FET is terminated by an on-timer, and the off-time is terminated when the feedback voltage VFB_AUX falls below the reference voltage (VAUX-ON). For a buck topology this type of hysteretic control provides stable operation if these two conditions are met:

  • Output voltage ripple is dominated by the resistive ESR component. The resistive ripple amplitude must be approximately five times the capacitive ripple amplitude to guarantee stable operation.
  • Output voltage ripple amplitude present at the FB_AUX pin must be greater than noise coupled onto this pin from other sources. For an output voltage ripple amplitude of 25 mV at the FB_AUX pin ensures that other sources of noise coupled to the pin can be assumed small

Aux transformer magnetising inductor ripple current amplitude is expressed by Equation 43.

Equation 43. GUID-7C836CE4-A91B-4AE5-869B-BD35CDB23773-low.gif

For a buck converter the capacitive component of output voltage ripple amplitude is expressed by Equation 92. The resistive component of output ripple voltage amplitude is expressed by Equation 44.

Equation 44. GUID-CE7C9B48-C65D-4D52-9383-9D74F06076AA-low.gif

Our condition for stable operation requires that Equation 45 and Equation 46 are both satisfied.

Equation 45. GUID-D916776C-8A3E-4650-B127-97E18DDF5E93-low.gif
Equation 46. GUID-F4896093-A956-4CF4-83AD-B3469D2C967F-low.gif

The method outlined above allows us to calculate the resistance (REsr) that must be present in series with the output capacitor (CAUX1) to provide stable operation of a buck converter. This simple method has disadvantages of high output voltage ripple amplitude and high dissipation in the series resistor REsr. The method is also not ideal for a flybuck topology, especially if most of the load current is drawn from the secondary winding. In this case much of the magnetising inductor current flows into the secondary output capacitor (CAUX2) and not the primary output capacitor (CAUX1) during the low-side FET conduction period (tOFF). The circuit of Figure 7-27 provides a better solution that is well suited to the flybuck topology. A series branch Rr – Cr is connected across LAUX. The controller applies the same PWM voltage across this series branch as appears across LAUX. Assuming most of the PWM voltage is dropped across Rr, the voltage across Cr has the almost the same shape and phase as the inductor current. The voltage ripple across Cr can be used to substitute the voltage across RESR and thus provide stable operation without the need for high output ripple and dissipation. By coupling this capacitor voltage signal directly to the FB_AUX pin we can achieve the same result as a large ESR resistor, but without the penalty of dissipation and high output voltage ripple amplitude. The method is suitable for a flybuck topology, since the down-slope of the magnetising current is synthesised, across Cr, and therefore available on the primary side to couple onto the FB_AUX pin.

GUID-6C7AEE13-3FBF-4031-807B-F61C2554015A-low.gif Figure 7-27 Minimum Ripple Configuration

The impedance of the capacitor generating the synthesised inductor current ripple signal, at the Aux switching frequency (fSW_AUX), must be low compared with the impedance of the RFBx divider network.

Equation 47. GUID-4DA45238-F3E8-4238-8354-B5B81D46E28A-low.gif

The synthesised inductor ripple, generated across Cr, is added to the ripple across the output capacitor (CAUX1). The resultant signal is coupled to the FB_AUX pin via capacitor Cac. The value of series resistor Rr is chosen to ensure the synthesised resistive ripple amplitude satisfies Equation 45 giving Equation 48.

Equation 48. GUID-30F4AA86-6FB4-4E78-A1AE-FCB1E44F2A9A-low.gif

Capacitor Cac couples the ripple signal directly onto the FB_AUX pin. Ensure that the value of this capacitor is at least five times greater than the value of Cr. This ratio ensures minimum attenuation and phase shift of the coupled ripple signal.

Equation 49. GUID-BF9659B8-4175-4B31-A649-AD4C49D04B45-low.gif