JAJSF96C April   2018  – October 2021 LM5036

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Undervoltage Lockout (UVLO)
      3. 7.3.3  Reference Regulator
      4. 7.3.4  Oscillator, Synchronized Input
      5. 7.3.5  Voltage-Mode Control
      6. 7.3.6  Primary-Side Gate Driver Outputs (LSG and HSG)
      7. 7.3.7  Half-Bridge PWM Scheme
      8. 7.3.8  Maximum Duty Cycle Operation
      9. 7.3.9  Pre-Biased Start-Up Process
        1. 7.3.9.1 Primary FETs Soft-Start Process
        2. 7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
      10. 7.3.10 Zero Duty Cycle Operation
      11. 7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
      12. 7.3.12 Reverse Current Protection
      13. 7.3.13 CBC Threshold Accuracy
      14. 7.3.14 Hiccup Mode Protection
      15. 7.3.15 Hiccup Mode Blanking
      16. 7.3.16 Over-Temperature Protection (OTP)
      17. 7.3.17 Over-Voltage / Latch (ON_OFF Pin)
      18. 7.3.18 Auxiliary Constant On-Time Control
      19. 7.3.19 Auxiliary On-Time Generator
      20. 7.3.20 Auxiliary Supply Current Limiting
      21. 7.3.21 Auxiliary Primary Output Capacitor Ripple
      22. 7.3.22 Auxiliary Ripple Configuration and Control
      23. 7.3.23 Asynchronous Mode Operation of Auxiliary Supply
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Input Transient Protection
        3. 8.2.2.3  Level-Shift Detection Circuit
        4. 8.2.2.4  Applications with VIN > 100-V
        5. 8.2.2.5  Applications without Pre-Biased Start-Up Requirement
        6. 8.2.2.6  UVLO Voltage Divider Selection
        7. 8.2.2.7  Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
        8. 8.2.2.8  SS Capacitor
        9. 8.2.2.9  SSSR Capacitor
        10. 8.2.2.10 Half-Bridge Power Stage Design
        11. 8.2.2.11 Current Limit
        12. 8.2.2.12 Auxiliary Transformer
        13. 8.2.2.13 Auxiliary Feedback Resistors
        14. 8.2.2.14 RON Resistor
        15. 8.2.2.15 VIN Pin Capacitor
        16. 8.2.2.16 Auxiliary Primary Output Capacitor
        17. 8.2.2.17 Auxiliary Secondary Output Capacitor
        18. 8.2.2.18 Auxiliary Feedback Ripple Circuit
        19. 8.2.2.19 Auxiliary Secondary Diode
        20. 8.2.2.20 VCC Diode
        21. 8.2.2.21 Opto-Coupler Interface
        22. 8.2.2.22 Full-Bridge Converter Applications
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Current Limit

Section 7.3.11 describes the CBC current limiting functionality in detail. Figure 8-7 illustrates the current limiting block diagram of the LM5036 controller. These are the five resistors associated with the current limiting function of the half-bridge converter:

  • RCS
  • R3
  • R2
  • RLIM
  • R1

Because R3 is equal to the equivalent resistance of R1 and R2 as given by Equation 13, there are four unknown resistor values to be determined.

GUID-E7084DE6-D8F5-49C3-8D81-28D635FB512D-low.gifFigure 8-7 Current Limiting Block

The value of current sense resistor RCS is determined based on the maximum power consumption requirement. Typically, the current sense resistor should consume less than 0.5% of the input power of the converter at the worst case scenario. The sense resistor conducts every alternate current pulse flowing in the primary winding. The power dissipated in the sense resistor is determined by Equation 61.

Equation 61. GUID-565013B6-5CB4-4DE5-99BF-0F0A8856B4A1-low.gif

The RMS current flowing in the primary winding may be calculated using Equation 62.

Equation 62. GUID-DE955F47-0FE1-4D46-90DC-994BFD9151A6-low.gif

Maximum loss in the current sense resistor will occur while maximum output current (ILIM) is delivered from minimum input voltage (VIN(min)). Evaluating Equation 62 gives Equation 63.

Equation 63. GUID-02A5565B-0E20-429A-A709-1578B6FDE921-low.gif

To achieve our target of dissipating less than 0.5% of maximum output power the current sense resistor must satisfy Equation 64.

Equation 64. GUID-4E466812-5FC2-4DC7-B575-D6C2D9550ADD-low.gif

In our example design the current sense resistor value selected is given in Equation 65.

Equation 65. GUID-1D0DDF11-9772-481E-9F73-40970AE5AAB2-low.gif
GUID-1C90EC28-4BA0-49B1-8799-6D2E414B9514-low.gif Figure 8-8 Main Converter Operating Waveforms

The resistor R1 is used to set the slope compensation magnitude. In LM5036 device, the slope of the compensation ramp is given by Equation 66. To eliminate sub-harmonic oscillation, set mC to at least one-half the down-slope of output inductor current transformed to the primary side across the current sense resistor, as given by Equation 67 and Equation 68. To damp the sub-harmonic oscillation after one cycle, mC must be set equal to one times the down-slope of the output inductor current. This configuration is known as deadbeat control. In LM5036 controller, the slope compensation signal is a saw-tooth current waveform of magnitude ISLOPE at the oscillator frequency (twice the switching frequency).

Equation 66. GUID-E8F1CE3F-EA9D-4910-8953-AB18D1DBC294-low.gif

where

  • mC is the slope of the compensation ramp
  • ISLOPE is the amplitude of the saw-tooth current signal used for slope compensation
Equation 67. GUID-CEB90310-0E22-49FA-8254-EE166E4283EB-low.gif

where

  • mL is the down-slope of the output inductor current transformed to the primary side
  • NP is the number of turns for the primary winding of the main transformer
  • NS is the number of turns for the secondary winding of the main transformer
  • VO is the output voltage of the half-bridge converter
  • LO is the output inductor value of the half-bridge converter
  • RCS is the current sense resistor value
Equation 68. GUID-A208CA89-56B4-4535-88C1-674C88EB7846-low.gif

Substituting Equation 66 and Equation 67 into Equation 68 gives an expression for the minimum value for resistor R1 to avoid sub-harmonic oscillation.

Equation 69. GUID-26C3ED29-624C-4E40-AF3B-5F4339ED6B83-low.gif

Doubling this value ensures deadbeat control. For this example design, the value given in Equation 70 are selected

Equation 70. GUID-20DA6BF9-F70D-45F1-B256-F5239A424491-low.gif

Values have now been selected for both RCS and R1. Values for RLIM and R2 are yet to be determined. These values define the peak current limit threshold and how this level varies with input voltage. Equation 20, Equation 21 and Equation 25 define the relationship between peak primary current limit and maximum output current. For this design example ignore IBiasOffset and VCSOffset, because these parameters have only a small effect on output current limit. Setting these parameters to zero calculates Equation 71, Equation 72 and Equation 73.

Equation 71. GUID-FCC3426E-FAA1-4C38-961C-C92348704477-low.gif
Equation 72. GUID-3D27B7F8-912D-420E-B4B4-F77164AB1407-low.gif
Equation 73. GUID-6C6D5D6D-40E4-442B-BC94-3D49F4A57228-low.gif

The output current limit varies with input voltage. This design example limits the output current to ILIM at the extremes of input voltage giving Equation 74 and Equation 75. This value limits the spread of output current limit across the range of input voltage.

Equation 74. GUID-D789AAD8-810C-419D-A7CD-B7AA242BFD8E-low.gif
Equation 75. GUID-908A2EA5-BD0E-463E-AAE6-43C7171DEA2D-low.gif

Solving Equation 74 and Equation 75 simultaneously yields values for resistors RLIM and R2.

Equation 76. GUID-3681ED12-D002-4FD9-B2EB-DD901365DBEB-low.gif
Equation 77. GUID-15F884CF-679A-4B20-BDE1-104E82A3E887-low.gif

Having determined values for R1 and R2, the value of resistor R3 is fixed by Equation 13.

The selected values for R2 and RLIM are given in Equation 78. Figure 8-9 presents the measured output current limit vs input voltage for the circuit presented in Figure 8-1. Figure 8-9 also presents the output current limit vs line for the same circuit predicted by Equation 71, Equation 72 and Equation 73. There is good agreement between measured and predicted results.

Equation 78. GUID-A98330AA-2DB5-4821-A947-42B79CCDFDFD-low.gif
GUID-1FE5038A-27E9-43D3-B77C-296BD4CF951B-low.gif Figure 8-9 Main Converter Measured vs Predicted Output Current Limit

If the magnitude of the leading-edge spike is excessive, add an additional filter capacitor CF to form an RC filter with R1, to reduce the high-frequency noise spike. Both the leading-edge blanking (tCSBLK) and the RC filter help to prevent false triggering of the CBC current limiting operation.

The circuit connected to the CS_POS pin may be approximated by the simplified circuit shown in Figure 8-10.

GUID-D6E288D5-FD9F-4FA9-8F78-F1FAB395D442-low.gif Figure 8-10 CS_POS Filter Circuit Model and Waveform

The voltage across the current sense resistor during the conduction period of the low-side MOSFET is represented by Equation 79.

Equation 79. GUID-8D02373F-48BF-41C3-9B4D-9AC87ED2B299-low.gif

Where IP0 is the primary current at the start of the on period of the lower switch, and m is the slope of the primary current during the on period.

Equation 80. GUID-9F4C8815-A790-471A-B90D-905418F73FD7-low.gif
Equation 81. GUID-946C0774-A029-4B2F-8BF7-250C9FA5536B-low.gif

The voltage across capacitor CF for the circuit shown is expressed by Equation 82.

Equation 82. GUID-7DD120D6-795B-4454-8ABD-E93A3A29C100-low.gif

Let us assume that the on period of the lower switch is more than four times longer than the time constant made up of CF and R1. In this case the exponential term of Equation 82 tends to zero and the voltage across capacitor CF at the end of the tON period may be expressed by Equation 83.

Equation 83. GUID-FDE0C9DD-2E68-400C-9F41-A694BCAD3B75-low.gif

Comparing Equation 79 and Equation 83 shows that capacitor CF introduces an error in the sensed peak current given by Equation 84.

Equation 84. GUID-08C8227A-1A8F-4BE1-97CD-C8ED59A177A5-low.gif

Hence, to ensure the error introduced by the filter capacitor is less than 2%, the value of capacitor CF should not exceed the value given by Equation 85.

Equation 85. GUID-9EF2C82E-C594-4CFD-A3C8-1574690462A0-low.gif

The Excel Calculator Tool can be used to facilitate the process of calculating all the external CBC component values.