JAJSQP5 july   2023 LMG2100R044

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Mismatch Measurement
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Control Inputs
      2. 9.3.2 Start-up and UVLO
      3. 9.3.3 Bootstrap Supply Voltage Clamping
      4. 9.3.4 Level Shift
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 VCC Bypass Capacitor
        2. 10.2.2.2 Bootstrap Capacitor
        3. 10.2.2.3 Power Dissipation
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
  13.   Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RAR|16
サーマルパッド・メカニカル・データ
発注情報

9.3.2 Start-up and UVLO

The LMG2100R044 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 9-1 VCC UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below)HILISW
VCC - VSS < VCCR during device start-upHLHi-Z
VCC - VSS < VCCR during device start-upLHHi-Z
VCC - VSS < VCCR during device start-upHHHi-Z
VCC - VSS < VCCR during device start-upLLHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upHLHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upLHHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upHHHi-Z
VCC - VSS < VCCR - VCC(hyst) after device start-upLLHi-Z
Table 9-2 VHB-HS UVLO Feature Logic Operation
CONDITION (VCC > VCCR for all cases below)HILISW
VHB-HS < VHBR during device start-upHLHi-Z
VHB-HS < VHBR during device start-upLHPGND
VHB-HS < VHBR during device start-upHHPGND
VHB-HS < VHBR during device start-upLLHi-Z
VHB-HS < VHBR - VHB(hyst) after device start-upHLHi-Z
VHB-HS < VHBR - VHB(hyst) after device start-upLHPGND
VHB-HS < VHBR - VHB(hyst) after device start-upHHPGND
VHB-HS < VHBR - VHB(hyst) after device start-upLLHi-Z