JAJSQ78A april   2023  – august 2023 LMH32401-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 絶対最大定格
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Gain = 2 kΩ
    6. 6.6 Electrical Characteristics: Gain = 20 kΩ
    7. 6.7 Electrical Characteristics: Both Gains
    8. 6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
    9. 6.9 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switched Gain Transimpedance Amplifier
      2. 7.3.2 Clamping and Input Protection
      3. 7.3.3 ESD Protection
      4. 7.3.4 Differential Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ambient Light Cancellation (ALC) Mode
      2. 7.4.2 Power-Down Mode (Multiplexer Mode)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Achieving the best performance with a high-frequency amplifier, such as the LMH32401-Q1, requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include the following:

  • Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the output pins can cause instability; whereas, parasitic capacitance on the input pin reduces the amplifier bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
  • Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times greater than the amplifiers maximum power supplies. Place the smallest-value capacitors on the same side as the DUT. If space constraints force the larger-value bypass capacitors to be placed on the opposite side of the PCB, then use multiple vias on the supply and ground side of the capacitors. This configuration provides a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be used on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling capacitors among several devices in the same area of the printed circuit board (PCB).