JAJSDF8B March 2017 – July 2019 LMK04616
PRODUCTION DATA.
The PLL2_RDIV_CLKEN Register supports PLL2 R-Divider enable.Back to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:1] | RSRVD | - | - | Reserved. |
[0] | PLL2_RDIV_CLKEN | RW | 0 | PLL2 R-Divider Clock Enable. |