JAJSDF8B March 2017 – July 2019 LMK04616
PRODUCTION DATA.
There are no external resistors and capacitors required for the low bandwidth PLL1. However, to introduce 3rd order pole in the loop, external capacitor C3 can be attached to the control voltage, which in combination with the on-chip resistor, creates a pole at the desired frequency. Recommended maximum value of C3 for PLL1 lock is 2.2 µF.