JAJSS15 November   2023 LMK3H0102

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
        5. 7.4.2.5 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Block Diagram Examples
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Example: Changing Output Frequency
      5. 8.2.5 Crosstalk
      6. 8.2.6 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
    2. 9.2 Decoupling Power Supply Inputs
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Device Registers
    1. 12.1 Register Maps
      1. 12.1.1  R0 Register (Address = 0x0) [reset = 0x0861]
      2. 12.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 12.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 12.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 12.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 12.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 12.1.7  R6 Register (Address = 0x6) [reset = 0x2AA0]
      8. 12.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 12.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 12.1.10 R9 Register (Address = 0x9) [reset = 0x0066]
      11. 12.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 12.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 12.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 12.1.14 R27 Register (Address = 0x1B) [reset = 0x0000]
      15. 12.1.15 R28 Register (Address = 0x1C) [reset = 0x0000]
      16. 12.1.16 R32 Register (Address = 0x20) [reset = 0x0000]
      17. 12.1.17 R33 Register (Address = 0x21) [reset = 0x0000]
      18. 12.1.18 R146 Register (Address = 0x92) [reset = 0x0000]
      19. 12.1.19 R147 Register (Address = 0x93) [reset = 0x0000]
      20. 12.1.20 R148 Register (Address = 0x94) [reset = 0x0000]
      21. 12.1.21 R238 Register (Address = 0xEE) [reset = 0x0000]
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Package Option Addendum
    2. 14.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • RER|16
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions


GUID-20231030-CA0I-MLR3-WRGJ-9SZBKZKSZK0N-low.svg
Figure 4-1 LMK3H0102 16-Pin TQFN Top View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
OUT0_P, OUT0_N8, 7OClock output 0. Supports LP-HCSL (85 Ω or 100 Ω), LVDS or 1.8-V/2.5-V/3.3-V LVCMOS.
OUT1_P, OUT1_N12, 11OClock output 1. Supports LP-HCSL (85 Ω or 100 Ω), LVDS or 1.8-V/2.5-V/3.3-V LVCMOS.
REF_CTRL (REF_CLK)15I/O

Multifunctional pin. At power up, the state of this pin is latched to select the functionality of Pin 2, Pin 3 and Pin 4. Pull low or leave floating for I2C mode or high for OTP mode prior to power-up. After power-up, this pin can be programmed as an additional LVCMOS output (REF_CLK), active-high CLK_READY signal (default), or disabled.

See REF_CTRL Operation for more details.

This pin has an 880-kΩ internal pulldown resistor.

OE1I

Global Output Enable. Active low. 2-state logic input pin.

This pin has a 75-kΩ internal pulldown resistor.

See Output Enable for more details.

  • Low/Floating: OUT0 and OUT1 enabled
  • High: OUT0 and OUT1 disabled
FMT_ADDR2I

Multifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for more details.

This pin has an 880-kΩ internal pulldown resistor.

  • I2C Mode: This pin selects the I2C address.
  • OTP Mode: This pin sets the output format.
OTP_SEL0/SCL, OTP_SEL1/SDA3, 4I, I/OMultifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for details. These pins have 880-kΩ internal pulldown resistors.
  • I2C Mode: These pins are the I2C clock and data connections.
  • OTP Mode: These pins select the OTP page.
VDD5, 14, 16P1.8-V, 2.5-V or 3.3-V device power supply. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
VDDO_0, VDDO_110, 13P1.8-V, 2.5-V or 3.3-V OUT0 and OUT1 power supply. If VDD is 1.8 V or 2.5 V, the VDDO pins must be the same voltage as VDD. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
NC6, 9N/A

No connect. Pins can be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings.

DAP17GGND
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
Table 4-2 BLOT
NAMENO.TYPE(1)DESCRIPTION
OUT0_N7OClock output 0. Supports LP-HCSL (85 Ω or 100 Ω), LVDS or 1.8-V/2.5-V/3.3-V LVCMOS.
OUT0_P8OClock output 0. Supports LP-HCSL (85 Ω or 100 Ω), LVDS or 1.8-V/2.5-V/3.3-V LVCMOS.
OUT1_N11OClock output 1. Supports LP-HCSL (85 Ω or 100 Ω), LVDS or 1.8-V/2.5-V/3.3-V LVCMOS.
OUT1_P12OClock output 1. Supports LP-HCSL (85 Ω or 100 Ω), LVDS or 1.8-V/2.5-V/3.3-V LVCMOS.
REF_CTRL 15I/O

Multifunctional pin. At power up, the state of this pin is latched to select the functionality of Pin 2, Pin 3 and Pin 4. Pull low or leave floating for I2C mode or high for OTP mode prior to power-up. After power-up, this pin can be programmed as an additional LVCMOS output (REF_CLK), active-high CLK_READY signal (default), or disabled.

See REF_CTRL Operation for more details.

This pin has an 880-kΩ internal pulldown resistor.

OE1I

Global Output Enable. Active low. 2-state logic input pin.

This pin has a 75-kΩ internal pulldown resistor.

See Output Enable for more details.

  • Low/Floating: OUT0 and OUT1 enabled
  • High: OUT0 and OUT1 disabled
FMT_ADDR2I

Multifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for more details.

This pin has a 75-kΩ internal pulldown resistor.

  • I2C Mode: This pin selects the I2C address.
  • OTP Mode: This pin sets the output format.
OTP_SEL0/SCL, 3IMultifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for more details.
  • I2C Mode: These pins are the I2C clock and data connections.
  • OTP Mode: These pins select the OTP page.
OTP_SEL1/SDA4 I/OMultifunctional pin. Functionality is determined by REF_CTRL (pin 15) at power up. See OTP Mode and I2C Mode for more details.
  • I2C Mode: These pins are the I2C clock and data connections.
  • OTP Mode: These pins select the OTP page.
VDD5P1.8-V, 2.5-V or 3.3-V device power supply. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
VDD14 P1.8-V, 2.5-V or 3.3-V device power supply. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
VDD16P1.8-V, 2.5-V or 3.3-V device power supply. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
VDDO_010P1.8-V, 2.5-V or 3.3-V OUT0 and OUT1 power supply. If VDD is 1.8 V or 2.5 V, the VDDO pins must be the same voltage as VDD. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
VDDO_113P1.8-V, 2.5-V or 3.3-V OUT0 and OUT1 power supply. If VDD is 1.8 V or 2.5 V, the VDDO pins must be the same voltage as VDD. A 0.1-µF capacitor must be placed as close to each of the pins as possible.
NC6N/A

No connect. Pins can be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings.

NC9N/A

No connect. Pins can be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings.

DAP–GGND