JAJSS15 November 2023 LMK3H0102
ADVANCE INFORMATION
Table 12-1 lists the LMK3H0102 Device registers. All register offset address not listed in Table 12-1 can be considered as reserved locations and the register contents must not be modified.
Address | Acronym | Section |
---|---|---|
0x0 | R0 | Go |
0x1 | R1 | Go |
0x2 | R2 | Go |
0x3 | R3 | Go |
0x4 | R4 | Go |
0x5 | R5 | Go |
0x6 | R6 | Go |
0x7 | R7 | Go |
0x8 | R8 | Go |
0x9 | R9 | Go |
0xA | R10 | Go |
0xB | R11 | Go |
0xC | R12 | Go |
0x1B | R27 | Go |
0x1C | R28 | Go |
0x20 | R32 | Go |
0x21 | R33 | Go |
0x92 | R146 | Go |
0x93 | R147 | Go |
0x94 | R148 | Go |
0xEE | R238 | Go |
Complex bit access types are encoded to fit into small table cells. Table 12-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WL |
W L |
Write Locked, requires R12[7:0] = 0x5B to unlock and write successfully |