7.3.1 Full Bandwidth Limitations

Although the LMP8350 has a unity gain bandwidth of over 200 MHz, it is primarily intended for lower sample rate, high-precision ADCs with baseband analog input signal bandwidths in the DC to <1 MHz range (not to be confused with sampling rate). The high open-loop bandwidth of the LMP8350 is used to provide ultra low distortion and fast settling times. Maximum power bandwidth is limited by the internal output common-mode feedback path, which is limited to 1 MHz to 5 MHz. Operation with input signals above 1 MHz with near full output swings can cause random shifts in the output common mode and possible AC instabilities. For this reason, the LMP8350 is not intended to be used wide bandwidth (> 1 MHz) signal paths. Single-ended inputs rely on the common-mode signal path and will have a bandwidth limited to that of the internal common-mode buffer.

7.3.2 ESD Protection

The LMP8350 is protected against electrostatic discharge (ESD) on all pins. The LMP8350 will survive 2000-V human body model and 200-V machine model events. Under normal operation, the ESD diodes have no effect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMP8350 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation.

7.4.1 Enable Pin and Power Mode Selection

The LMP8350 is equipped with a four-level enable (EN) pin to select one of three power modes or shutdown. These modes are selected by applying the appropriate voltage to the EN pin.

Each power level has a corresponding performance level. The high power mode will have the best overall BW and distortion performance, but at the cost of higher supply current and some DC accuracy. The low power mode has the lowest supply current, but with a noticeable loss of AC performance and output drive capabilities. The mid-power mode provides the best balance of AC and precision DC specifications. In disable mode, the amplifier is shutdown and the output stage goes into a high impedance state. Table 1 summarizes these performance trade-offs.

To set the mode, internally the voltage at the EN pin is compared against the total supply voltage (V_S) and sets the current consumption as shown in the table below. The EN pin voltage is referenced to the V- pin.

The enable pin should not be allowed to float. If the enable pin is not used it can be tied to V+ to select the high power mode or set with two resistors.

Each power setting has a ±400-mV tolerance at each level, though TI recommends to keep the set voltage within the center of the range as performance may vary near the transition zones.

During shutdown, both outputs are in a high impedance state, so the feedback and gain set resistors will then set the input and output impedance of the circuit. For this reason input to output isolation will be poor in the disabled state.

The voltage at the EN pin can be generated with a resistive voltage divider or a buffer connected to a voltage source or a DAC. Figure 34 shows how to generate EN voltage with a resistive voltage divider.

Values of R_A and R_B can be calculated to achieve the voltages in Table 2, however their sum should be below
50 kΩ to keep the voltage at the enable pin stable. Recommended values for R_A and R_B are given in Table 3.

7.4.2 V_OCM Pin and Output Common-Mode Setting

Output common-mode voltage is set by the V_OCM pin. Both outputs will be offset in the same direction (phase) by an amount equal to the applied V_OCM voltage.

The V_OCM pin, if left unconnected, will self-bias to mid-supply. Two internal 60-kΩ resistors set this midpoint. These resistors are shown in Figure 28.

Figure 28. V_OCM Internal Bias Circuit

The equivalent resistance looking into the V_OCM pin will look like 30 kΩ to mid-supply, plus about ±700 nA for internal base currents (which scales with power mode and supply current). If left floating, the V_OCM input should be bypassed to ground with a 0.1-µF ceramic capacitor.

If a different output common-mode voltage is desired, the V_OCM pin should be driven by a clean, low impedance source to override the internal divider resistors. The V_OCM pin should be bypassed to ground with a 0.1-µF ceramic capacitor. It should be noted that any signal or noise-coupling into the V_OCM will be passed as common-mode noise and may result in the loss of dynamic range, degraded CMRR, degraded balance and higher distortion. The V_OCM pin is primarily intended as a DC bias path and is not intended for use as a signal path.

For applications that can tolerate slight shifts in the V_OCMvoltage over temperature, it is also possible to use a single resistor to program the V_OCM voltage by paralleling one of the internal resistors to change the ratio.