10.1 Layout Guidelines

While the main signal path frequencies may be fairly low, the ultra low distortion and settling time specifications rely on wide internal bandwidths. Precautions usually taken for high-speed amplifiers should be followed to maintain the best settling times and lowest distortion specifications. In order to get maximum benefit from the differential circuit architecture, board layout and component selection is very critical. The circuit board should have low a inductance ground plane and well bypassed broad supply lines. External components should be leadless surface mount types. The feedback network and output matching resistors should be composed of short traces and precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the amplifier as should the supply bypass capacitors.

The LMP8350 is sensitive to parasitic capacitances on the outputs. Ground and power plane metal should be removed from beneath the amplifier and from beneath R_F and R_G.

With any differential signal path symmetry is very important. Even small amounts of asymmetry will contribute to distortion and balance errors. Special attention should be paid to where the bypass capacitors are grounded, as this also affects settling and distortion performance.

The LMH730154 evaluation board is an example of good layout techniques. Evaluation boards are available for purchase through the product folder on TI’s website.

10.2 Layout Example

Figure 38. Layout Example

10.3 Power Dissipation

The LMP8350 is optimized for maximum performance in the small form factor of the standard SOIC package, and is essentially a dual-channel amplifier. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the T_JMAX of 150°C is never exceeded due to the overall power dissipation.

Follow these steps to determine the Maximum power dissipation for the LMP8350:

1. Calculate the quiescent (no-load) power using Equation 5 (Be sure to include any current through the feedback network if V_OCM is not mid-rail.):
Equation 5. P_AMP = I_CC× (V_S)
where
• V_S = V⁺ – V⁻.
2. Calculate the RMS power dissipated in each of the output stages using Equation 6:
Equation 6. P_D (rms) = rms ((V_S – V⁺_OUT) × I⁺_OUT) + rms ((V_S − V⁻_OUT) × I⁻_OUT)
where
• V_OUT and I_OUT are the voltage and the current measured at the output pins of the differential amplifier as if they were single ended amplifiers and V_S is the total supply voltage.
3. Calculate the total RMS power: P_T = P_AMP + P_D.

The maximum power that the LMP8350 package can dissipate at a given temperature can be derived from Equation 7:

10.4 Evaluation Board

Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 (SNOA367) for more information). Texas Instruments suggests the following evaluation boards in Table 4 as a guide for high-frequency layout and as an aid in device testing and characterization: