JAJSG01D June   2012  – August 2018 LMZ20502

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      VOUT = 1.8V、自動モードでの標準的な効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Nano Scale Package
      2. 7.3.2 Internal Synchronous Rectifier
      3. 7.3.3 Current Limit Protection
      4. 7.3.4 Start-Up
      5. 7.3.5 Dropout Behavior
      6. 7.3.6 Power Good Flag Function
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Setting The Output Voltage
        3. 8.2.1.3 Output and Feed-Forward Capacitors
        4. 8.2.1.4 Input Capacitors
        5. 8.2.1.5 Maximum Ambient Temperature
        6. 8.2.1.6 Options
      2. 8.2.2 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Soldering Information
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
      3. 11.1.3 ドキュメントのサポート
        1. 11.1.3.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIL|8
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Dropout Behavior

When the input voltage is close to the output voltage the regulator will operate at very large duty cycles. Normal time delays of the internal circuits prevents the attainment of controlled duty cycles near 100%. In this condition the LMZ20502 will skip switching cycles in order to maintain regulation with the highest possible input-to-output ratio. Some increase in output voltage ripple may appear as the regulator skips cycles. As the input voltage gets closer to the output voltage, the regulator will eventually reach 100% duty cycle, with the high side switch turned on. The output will then follow the input voltage minus the drop across the high side switch and inductor resistance. Figure 11 and Figure 12 show typical drop-out behavior for output voltages of 2.5 V and 3.3 V.

Since the internal gate drive levels of the LMZ20502 are dependent on input voltage, the Rdson of the power FETs will increase at low input voltages. This will result in degraded efficiency at output currents of greater than 1 A and input voltages below about 2.9 V. Also, combinations of low input voltage and high output voltage increases the effective switch duty cycle which may result in increased output voltage ripple.

LMZ20502 droput_2p5_snvs852.pngFigure 11. Typical Drop-Out Behavior, VOUT = 2.5 V
LMZ20502 drop_out.pngFigure 12. Typical Drop-Out Behavior, VOUT = 3.3 V