JAJSF83E June   2013  – February 2020 LMZ31707

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     アプリケーション概略図
  4. 改訂履歴
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Specifications
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
  6. Device Information
    1. 6.1 Functional Block Diagram
    2.     Pin Functions
  7. Typical Characteristics (PVIN = VIN = 12 V)
  8. Typical Characteristics (PVIN = VIN = 5 V)
  9. Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  10. 10Application Information
    1. 10.1  Adjusting the Output Voltage
    2. 10.2  Capacitor Recommendations for the LMZ31707 Power Supply
      1. 10.2.1 Capacitor Technologies
        1. 10.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 10.2.1.2 Ceramic Capacitors
        3. 10.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 10.2.2 Input Capacitor
      3. 10.2.3 Output Capacitor
    3. 10.3  Transient Response
    4. 10.4  Transient Waveforms
    5. 10.5  Application Schematics
    6. 10.6  Custom Design With WEBENCH® Tools
    7. 10.7  VIN and PVIN Input Voltage
    8. 10.8  3.3 V PVIN Operation
    9. 10.9  Power Good (PWRGD)
    10. 10.10 SYNC_OUT
    11. 10.11 Parallel Operation
    12. 10.12 Light Load Efficiency (LLE)
    13. 10.13 Power-Up Characteristics
    14. 10.14 Pre-Biased Start-up
    15. 10.15 Remote Sense
    16. 10.16 Thermal Shutdown
    17. 10.17 Output On/Off Inhibit (INH)
    18. 10.18 Slow Start (SS/TR)
    19. 10.19 Overcurrent Protection
    20. 10.20 Synchronization (CLK)
    21. 10.21 Sequencing (SS/TR)
    22. 10.22 Programmable Undervoltage Lockout (UVLO)
    23. 10.23 Layout Considerations
    24. 10.24 EMI
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Synchronization (CLK)

An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.5 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 34.

Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by the RT resistor (RRT).

LMZ31707 slvsBC6_RTSync.gifFigure 34. RT/CLK Configuration

The switching frequency must be selected based on the output voltage of the device being synchronized. Table 7 shows the allowable frequencies for a given range of output voltages. The allowable switching frequency changes based on the maximum output current (IOUT) of an application. The table shows the VOUT range when IOUT ≤ 7 A, 6 A, and 5 A. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three LMZ31707 devices with output voltages of 1.0 V, 1.2 V, and 1.8 V, all powered from PVIN = 12 V. Table 7 shows that all three output voltages should be synchronized to 300 kHz.

Table 7. Allowable Switching Frequency versus Output Voltage

SWITCHING FREQUENCY (kHz) PVIN = 12 V PVIN = 5 V
VOUT RANGE (V) VOUT RANGE (V)
IOUT ≤ 7 A IOUT ≤ 6 A IOUT ≤ 5 A IOUT ≤ 7 A IOUT ≤ 6 A IOUT ≤ 5 A
200 0.6 - 1.2 0.6 - 1.5 0.6 - 1.9 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
300 0.8 - 1.9 0.8 - 2.6 0.8 - 3.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
400 1.1 - 2.7 1.1 - 4.1 1.1 - 5.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
500 1.4 - 3.9 1.4 - 5.5 1.4 - 5.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3
600 1.6 - 5.5 1.6 - 5.5 1.6 - 5.5 0.9 - 4.2 0.6 - 4.2 0.9 - 4.2
700 1.9 - 5.5 1.8 - 5.5 1.8 - 5.5 0.9 - 4.1 0.9 - 4.1 1.0 - 4.1
800 2.1 - 5.5 2.1 - 5.5 2.1 - 5.5 1.2 - 4.0 1.0 - 4.0 1.0 - 4.0
900 2.4 - 5.5 2.4 - 5.5 2.4 - 5.5 1.2 - 3.9 1.1 - 3.9 1.1 - 3.9
1000 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 1.2 - 3.8 1.2 - 3.8 1.2 - 3.8
1100 2.9 - 5.5 2.9 - 5.5 2.9 - 5.5 1.5 - 3.7 1.4 - 3.7 1.4 - 3.7
1200 3.2 - 5.5 3.2 - 5.5 3.2 - 5.5 1.5 - 3.6 1.5 - 3.6 1.5 - 3.6