JAJSCR1 November   2016 LP5922

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Input and Output Capacitors
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage
      2. 7.3.2 Enable
      3. 7.3.3 Output Automatic Discharge
      4. 7.3.4 Programmable Soft Start and Noise Reduction
      5. 7.3.5 Internal Current Limit
      6. 7.3.6 Thermal Overload Protection
      7. 7.3.7 Power Good Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Undervoltage Lockout (UVLO)
      3. 7.4.3 Minimum Operating Input Voltage
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor, CIN
        3. 8.2.2.3 Output Capacitor, COUT
        4. 8.2.2.4 Soft-Start and Noise-Reduction Capacitor, CSS/NR
        5. 8.2.2.5 Feed-Forward Capacitor, CFF
        6. 8.2.2.6 No-Load Stability
        7. 8.2.2.7 Power Dissipation
        8. 8.2.2.8 Estimating Junction Temperature
        9. 8.2.2.9 Recommended Continuous Operating Area
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Description

Overview

The LP5922 is a low-noise, high PSRR, low-dropout regulator capable of sourcing a 2-A load. The LP5922 can operate down to 1.3-V input voltage and 0.5-V output voltage. This combination of low noise, high PSRR, and low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive communication components to battery-powered system.

The LP5922 block diagram contains several features, including:

  • Low-noise, 0.5-V reference
  • Internal protection circuit, such as current limit and thermal shutdown
  • Programmable soft-start circuit
  • Power Good output

Functional Block Diagram

LP5922 FBD_snvsag0.gif

Feature Description

Output Voltage

The LP5922 output voltage can be set to any value from 0.5 V to 5 V using two external resistors shown as RUPPER and RLOWER in Figure 15. The value for the RLOWER should be less than or equal to 100 kΩ for good loop compensation. RUPPER can be selected for a given VOUT using Equation 1:

Equation 1. LP5922 eq01_snvsag0.gif

where

  • VFB = 0.5 V

Enable

The LP5922 EN pin is internally held low by a 2-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is activated.

Output Automatic Discharge

The LP5922 output employs an internal 400-Ω (typical) pulldown resistance to discharge the output capacitor when the EN pin is low, and the device is disabled.

Programmable Soft Start and Noise Reduction

The output voltage of LP5922 ramps up linearly in a constant slew rate until reaching the target regulating voltage after a stable VIN (greater than VOUT + VDO) is supplied and EN pin is pulled high. The slew rate of VOUT ramping is programmable by an external capacitor on the SS/NR pin; therefore, the duration for soft-start period is programmable as well. Once the LP5922 is enabled, the SS/NR pin sources a constant 6-µA current to charge the external CSS/NR capacitor until the voltage at the SS/NR pin reaches 98% of the internal reference voltage (VREF) of 500 mV typical. The final 2% of CSS/NR charge is determined by a RC time constant. During the soft-start period, the current flowing into the IN pin primarily consists of the sum of the load current at the LDO output and the charging current into the output capacitor. The soft-start period can be calculated by Equation 2:

Equation 2. LP5922 eq02_snvsag0.gif

where

  • VFB = 0.5 V - this is the voltage that CSS/NR charges to;
  • CSS/NR is the value of the capacitor connected between the SS/NR pin and ground; and
  • ISS = 6.2 µA is the typical charging current to the SS/NR pin during start-up period.

The recommended value for CSS/NR is 100 nF or larger. Equation 2 is most accurate for these values. The CSS/NR capacitor is also the filter capacitor for internal reference for noise reduction purpose. An integrated resistor and the CSS/NR capacitor structure a RC low-pass filter to remove the noise on the internal reference voltage.

Internal Current Limit

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.

Thermal Overload Protection

Thermal shutdown disables the output when the junction temperature rises to TSD level, which allows the device to cool. When the junction temperature cools by ΔTSD, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

The internal protection circuitry of the LP5922 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the LP5922 into thermal shutdown degrades device reliability.

Power Good Output

The LP5922 has a Power-Good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages (low impedance to GND). When the output voltage rises above the PG threshold voltage (PGHTH), the PG pin becomes high-impedance. By connecting a pullup resistor to an external supply, any downstream device can receive PG as a logic signal. User must make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices; use a pullup resistor from 10 kΩ to 100 kΩ for best results.

In Power-Good function, the PG output pin pulled high immediatelly after output voltage rises above the PG threshold voltage.

Device Functional Modes

Enable (EN)

The LP5922 enable (EN) pin is internally held low by a 2-MΩ resistor to GND. If the EN pin is open the output is OFF. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuit is activated. Any charge on the OUT pin is discharged to GND through the internal pulldown resistance.

Undervoltage Lockout (UVLO)

The LP5922 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP5922 disabled while a rising VIN is less than 1.2 V (typical). The rising UVLO threshold is approximately 100 mV below the recommended minimum operating VIN of 1.3 V.

Minimum Operating Input Voltage

The LP5922 internal circuit is not fully functional until VIN is at least 1.3 V. The output voltage is not regulated until VIN has reached at least the greater of 1.3 V or (VOUT + VDO).