SNVS542E May   2008  – June 2016 LP8900

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Default Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable (EN)
      2. 8.4.2 Minimum Operating Input Voltage (VIN)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Capacitors
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 No-Load Stability
        5. 9.2.2.5 Capacitor Characteristics
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 DSBGA Mounting
    4. 11.4 DSBGA Light Sensitivity
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

YZR Package
6-Pin DSBGA
LP8900 30039306.gif

Pin Functions

PIN TYPE DESCRIPTION
NUMBER NAME
A1 EN1 I Enable input; enables the regulator when ≥ 1.2 V. Enable Input has an internal 3-MΩ pulldown resistor to GND.
Disables the regulator when ≤ 0.4 V.
A2 OUT1 O Voltage output. A low ESR ceramic capacitor must be connected from this pin to GND. (See Application and Implementation.) Connect this output to the load circuit.
B1 GND G Common ground.
B2 IN I Voltage supply input. A 1-µF capacitor must be connected from this pin to GND.
C1 EN2 I Enable input; enables the regulator when ≥ 1.2 V. Enable input has an internal 3-MΩ pulldown resistor to GND.
Disables the regulator when ≤ 0.4 V.
C2 OUT2 O Voltage output. A low ESR ceramic capacitor must be connected from this pin to GND. (See Application and Implementation.) Connect this output to the load circuit.