over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT |
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VeREF+ | Reference input voltage range | DAC12IR = 0(1) (2) | 2.2 V, 3 V | | AVCC / 3 | AVCC + 0.2 | V |
DAC12IR = 1(3) (4) | | AVCC | AVCC + 0.2 |
Ri(VREF+), Ri(VeREF+) | Reference input resistance | DAC12_0 IR = DAC12_1 IR = 0 | 2.2 V, 3 V | 20 | | | MΩ |
DAC12_0 IR = 1, DAC12_1 IR = 0 | | 48 | | kΩ |
DAC12_0 IR = 0, DAC12_1 IR = 1 | | 48 | |
DAC12_0 IR = DAC12_1 IR = 1, DAC12_0 SREFx = DAC12_1 SREFx(5) | | 24 | |
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC – VE(O)) / (3 × (1 + EG)).
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC – VE(O)) / (1 + EG).
(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance.