JAJSEA5D December   2017  – October 2019 OPA207

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      非常に低い0.1Hz～10Hzのノイズ
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Input Protection
      3. 7.3.3 ESD Protection
      4. 7.3.4 Input Stage Linearization
      5. 7.3.5 Rail-to-Rail Output
      6. 7.3.6 Low Input Bias Current
      7. 7.3.7 Slew Boost
      8. 7.3.8 EMI Rejection Ratio (EMIRR)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical OPA207 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Precision Low-Side Current Sensing
      3. 8.2.3 Precision Buffer With Increased Output Current
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH Filter Designerツール
        2. 11.1.1.2 TINA-TI(無料のダウンロード・ソフトウェア)
        3. 11.1.1.3 TI Precision Designs
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
OPA207 C002_DC.png
Figure 1. Input Referred Offset Voltage Distribution
OPA207 OpenLoopGain_Phase.gif
Figure 3. Open-Loop Gain and Phase vs Frequency
OPA207 PSRR_CMRR.gif
Figure 5. Power Supply Rejection Ratio and Common-Mode Rejection Ratio vs Frequency
OPA207 FPBW.gif
Figure 7. Full Power Bandwidth
OPA207 Noise_10Sec_p1_10Hz.gif
Figure 9. 0.1-Hz to 10-Hz Noise Voltage
OPA207 OPA207_THDNvAmp_1kHz.gif
Figure 11. Total Harmonic Distortion + Noise vs Output Amplitude
OPA207 OPA207_OSvCload_Gp1.gif
G = +1 V/V
Figure 13. Overshoot vs Capacitive Load
OPA207 SmallSignal_G1_Cload.gif
G = +1 V/V
Figure 15. Small-Signal Step Response
OPA207 SmallSignal_G-1_Cload.gif
G = –1 V/V
Figure 17. Small-Signal Step Response
OPA207 PosOverloadRecovery.gif
Figure 19. Overload Recovery From Positive Overload
OPA207 SettlingTime.gif
VOUT = 3 VRMS
Figure 21. Settling Time
OPA207 C003_DC.png
Figure 23. Input Offset Voltage vs Input Common-mode Voltage
OPA207 C004_DC.png
Figure 25. Quiescent Current vs Power Supply Voltage
OPA207 C009A_DC.png
Figure 27. Output Voltage vs Output Current (Sourcing)
OPA207 C010_DC.png
Figure 29. Input Offset Voltage vs Temperature
OPA207 C005_DC.png
Figure 31. Open Loop Gain vs Temperature
OPA207 C012_DC.png
Figure 33. Power Supply Rejection Ratio vs Temperature
OPA207 C008_DC.png
Figure 35. Output Short Circuit Current vs Temperature
OPA207 C001_DC.png
Figure 2. Input Referred Offset Voltage Drift Distribution
OPA207 ClosedLoopGain.gif
Figure 4. Closed Loop Gain vs Frequency
OPA207 Open_Loop_Output_Z.gif
Figure 6. Open-Loop Output Impedance vs Frequency
OPA207 OPA207_Vnoise.gif
Figure 8. Input Voltage Noise Spectral Density vs Frequency
OPA207 Current_Noise.gif
Figure 10. Input Current Noise vs Frequency
OPA207 OPA207_THDNvFreq_3VRMS.gif
VOUT = 3 VRMS
Figure 12. Total Harmonic Distortion + Noise vs Frequency
OPA207 OPA207_OSvCload_Gn1.gif
G = –1 V/V
Figure 14. Overshoot vs Capacitive Load
OPA207 LargeSignal_G1_Cload.gif
G = +1 V/V
Figure 16. Large-Signal Step Response
OPA207 LargeSignal_G-1_Cload.gif
G = –1 V/V
Figure 18. Large-Signal Step Response
OPA207 NegOverloadRecovery.gif
Figure 20. Overload Recovery from Negative Overload
OPA207 NoPhaseReversal.gif
VOUT = 3 VRMS
Figure 22. No Phase Reversal
OPA207 C013_DC.png
Figure 24. Input Bias Current vs Input Common-mode Voltage
OPA207 C017_DC.png
Figure 26. Input Offset Voltage vs Power Supply Voltage
OPA207 C009B_DC.png
Figure 28. Output Voltage vs Output Current (Sinking)
OPA207 C014_DC.png
Figure 30. Input Bias Current vs Temperature
OPA207 C011_DC.png
Figure 32. Common-Mode Rejection Ratio vs Temperature
OPA207 C007_DC.png
Figure 34. Quiescent Current vs Temperature