JAJSGX7 February   2019 OPA2356-EP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Output Drive
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 OPA2356-EP Design Procedure
            1. 8.2.1.2.2.1 Optimizing the Transimpedance Circuit
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High-Impedance Sensor Interface
      3. 8.2.3 Driving ADCs
      4. 8.2.4 Active Filter
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at TA = –55°C to 125°C, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V ±2 ±9 mV
TA = –55°C to 125°C ±15
ΔVOS/ΔT Offset voltage drift over temperature TA = –55°C to 125°C ±7 µV/°C
PSRR Offset voltage drift vs power supply VS = 2.7 V to 5.5 V,
VCM = VS / 2 – 0.15 V		 ±80 ±350 µV/V
INPUT BIAS CURRENT
IB Input bias current 3 ±50 pA
IOS Input offset current ±1 ±50 pA
NOISE
Vn Input voltage noise density f = 1 MHz 5.8 nV/√Hz
In Current noise density f = 1 MHz 50 fA/√Hz
INPUT VOLTAGE RANGE
VCM Input common-mode voltage range (V–) – 0.1 (V+) – 1.5 V
CMRR Input common-mode rejection ratio VS = 5.5 V, –0.1 V < VCM < 4 V 66 80 dB
TA = –55°C to 125°C 66
INPUT IMPEDANCE
Differential input impedance 1013 || 1.5 Ω || pF
Common-mode input impedance 1013 || 1.5 Ω || pF
OPEN-LOOP GAIN
Open-loop gain VS = 5 V, 0.4 V < VO < 4.6 V, TA = –55°C to 125°C 80 dB
FREQUENCY RESPONSE
f–3dB Small-signal bandwidth G = 1, VO = 100 mVp-p, RF = 0 Ω 450 MHz
G = 2, VO = 100 mVp-p, RL = 50 Ω 100
G = 2, VO = 100 mVp-p, RL = 150 Ω 170
G = 2, VO = 100 mVp-p, RL = 1 kΩ 200
GBW Gain-bandwidth product G = 10, RL = 1 kΩ 200 MHz
f0.1dB Bandwidth for 0.1-dB gain flatness G = 2, VO = 100 mVp-p, RF = 560 Ω 75 MHz
SR Slew rate VS = 5 V, G = 2, 4-V output step 300 V/µs
–360
Rise and fall times G = 2, VO = 200 mVp-p, 10% to 90% 2.4 ns
G = 2, VO = 2 Vp-p, 10% to 90% 8
Settling time 0.1% VS = 5 V, G = 2, 2-V output step 30 ns
0.01% 120
Overload recovery time VIN × Gain = VS 8 ns
Harmonic distortion Second harmonic G = 2, f = 1 MHz, VO = 2 Vp-p,
RL = 200 Ω		 –81 dBc
Third harmonic –93
Differential gain error NTSC, RL = 150 Ω 0.02%
Differential phase error NTSC, RL = 150 Ω 0.05 °
Channel-to-channel crosstalk f = 5 MHz –90 dB
OUTPUT
Voltage output swing from rail VS = 5 V, RL = 150 Ω, AOL > 84 dB 0.2 0.3 V
VS = 5 V, RL = 1 kΩ 0.1
IO = ±100 mA 0.8 1
IO Continuous output current(1) ±60 mA
IO Peak output current(1) VS = 5 V ±100 mA
VS = 3 V ±80
Short-circuit current 250 mA
–200
Closed-loop output impedance 0.02 Ω
POWER SUPPLY
IQ Quiescent current (per amplifier) VS = 5 V, IO = 0 V 8.3 11 mA
TA = –55°C to 125°C 14
THERMAL SHUTDOWN
Junction temperature Shutdown 160 °C
Reset from shutdown 140
(1) See Figure 20.