JAJSCQ6A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA_SYNCH_ERR_EN | CHA_CRC_ERR_EN | CHA_UNC_ECC_ERR_EN | CHA_COR_ECC_ERR_EN | CHA_LLP_ERR_EN | CHA_SOT_BIT_ERR_EN | Reserved | PLL_UNLOCK_EN |
R/W | R/W | R/W | R/W | R/W | R/W | R | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CHA_SYNCH_ERR_EN | R/W | 0 | 0 – CHA_SYNCH_ERR is masked
1 – CHA_SYNCH_ERR is enabled to generate IRQ events |
6 | CHA_CRC_ERR_EN | R/W | 0 | 0 – CHA_CRC_ERR is masked
1 – CHA_CRC_ERR is enabled to generate IRQ events |
5 | CHA_UNC_ECC_ERR_EN | R/W | 0 | 0 – CHA_UNC_ECC_ERR is masked
1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events |
4 | CHA_COR_ECC_ERR_EN | R/W | 0 | 0 – CHA_COR_ECC_ERR is masked
1 – CHA_COR_ECC_ERR is enabled to generate IRQ events |
3 | CHA_LLP_ERR_EN | R/W | 0 | 0 – CHA_LLP_ERR is masked
1 – CHA_ LLP_ERR is enabled to generate IRQ events |
2 | CHA_SOT_BIT_ERR_EN | R/W | 0 | 0 – CHA_SOT_BIT_ERR is masked
1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events |
1 | Reserved | R | Reserved | |
0 | PLL_UNLOCK_EN | R/W | 0 | 0 – PLL_UNLOCK is masked
1 – PLL_UNLOCK is enabled to generate IRQ events |