JAJSFO1G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     標準アプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 Initialization Sequence

Use the following initialization sequence to setup the SN65DSI84. This sequence is required for proper operation of the device. Steps 9 through 11 in the sequence are optional.

Also see to Figure 6.

Table 2. Initialization Sequence

INITIALIZATION SEQUENCE NUMBER INITIALIZATION SEQUENCE DESCRIPTION
Init seq 1 Power on
Init seq 2 After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state
Init seq 3 Set EN pin to Low
Wait 10 ms (1)
Init seq 4 Tie EN pin to High
Wait 10 ms (1)
Init seq 5 Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not functional until the CSR registers are initialized)
Init seq 6 Set the PLL_EN bit (CSR 0x0D.0)
Wait 10 ms (1)
Init seq 7 Set the SOFT_RESET bit (CSR 0x09.0)
Wait 10 ms (1)
Init seq 8 Change DSI data lanes to HS state and start DSI video stream
Wait 5 ms (1)
Init seq 9 Read back all resisters and confirm they were correctly written
Init seq 10 Write 0xFF to CSR 0xE5 to clear the error registers
Wait 1 ms (1)
Init seq 11 Read CSR 0xE5. If CSR 0xE5!= 0x00, then go back to step #2 and re-initialize
(1) Minimum recommended delay. It is fine to exceed these.