JAJSCG0A September   2016  – November 2016 SN65HVD233-Q1 , SN65HVD234-Q1 , SN65HVD235-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: Driver
    6. 8.6  Electrical Characteristics: Receiver
    7. 8.7  Switching Characteristics: Driver
    8. 8.8  Switching Characteristics: Receiver
    9. 8.9  Switching Characteristics: Device
    10. 8.10 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1 Diagnostic Loopback (SN65HVD233-Q1)
      2. 10.3.2 Autobaud Loopback (SN65HVD235-Q1)
      3. 10.3.3 Slope Control
      4. 10.3.4 Standby
      5. 10.3.5 Thermal Shutdown
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Bus Loading, Length and Number of Nodes
        2. 11.2.1.2 CAN Termination
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curve
    3. 11.3 System Example
      1. 11.3.1 ISO 11898 Compliance of SN65HVD23x-Q1 Family of 3.3-V CAN Transceivers
        1. 11.3.1.1 Introduction
        2. 11.3.1.2 Differential Signal
        3. 11.3.1.3 Common-Mode Signal
        4. 11.3.1.4 Interoperability of 3.3-V CAN in 5-V CAN Systems
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 関連リンク
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Parameter Measurement Information

SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_dri_SLLSES4.gif Figure 12. Driver Voltage, Current, and Test Definition
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_bus_lls557.gif Figure 13. Bus Logic State Voltage Definitions
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_driv_SLLSES4.gif Figure 14. Driver VOD
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_dtc_SLLSES4.gif
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_rece_SLLSES4.gif Figure 16. Receiver Voltage and Current Definitions
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_rectc_SLLSES4.gif
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT MEASURED
VCANH VCANL RXD |VID|
–6.1 V –7 V L VOL 900 mV
12 V 11.1 V L 900 mV
–1 V –7 V L 6 V
12 V 6 V L 6 V
–6.5 V –7 V H VOH 500 mV
12 V 11.5 V H 500 mV
–7 V –1 V H 6 V
6 V 12 V H 6 V
Open Open H X
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_testc_SLLSES4.gif

NOTE:

This test is conducted to test survivability only. Data stability at the RXD output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_tens_SLLSES4.gif

NOTE:

All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 19. ten(s) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_tenz_SLLSES4.gif Figure 20. ten(z) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_vocpp_SLLSES4.gif Figure 21. VOC(pp) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_tloop_SLLSES4.gif Figure 22. t(loop) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_tlbk_SLLSES4.gif Figure 23. t(LBK) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_tab1_SLLSES4.gif Figure 24. t(AB1) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_tab2_SLLSES4.gif Figure 25. t(AB2) Test Circuit and Voltage Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_los_SLLSES4.gif Figure 26. IOS Test Circuit and Waveforms
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 pmi_comm_SLLSES4.gif

NOTE:

All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 27. Common-Mode Voltage Rejection
SN65HVD233-Q1 SN65HVD234-Q1 SN65HVD235-Q1 sch_diag_SLLSES4.gif Figure 28. Equivalent Input and Output Schematic Diagrams