JAJSF09B February   2015  – April 2015 SN65LVDS93A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Up Sequence
        2. 9.2.2.2 Signal Connectivity
        3. 9.2.2.3 PCB Routing
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Power and Ground Planes
      3. 11.1.3 Traces, Vias, and Other PCB Components
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 商標
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) See Figure 10, tC = 10ns,
|Input clock jitter| < 25ps (2) 		-0.1 0 0.1 ns
t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1/7 tc - 0.1 1/7 tc + 0.1 ns
t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) 2/7 tc - 0.1 2/7 tc + 0.1 ns
t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) 3/7 tc - 0.1 3/7 tc + 0.1 ns
t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) 4/7 tc - 0.1 4/7 tc + 0.1 ns
t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) 5/7 tc - 0.1 5/7 tc + 0.1 ns
t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) 6/7 tc - 0.1 6/7 tc + 0.1 ns
tc(o) Output clock period tc ns
Δtc(o) Output clock cycle-to-cycle jitter (3) tC = 10ns; clean reference clock, see Figure 11 ±26 ps
tC = 10ns with 0.05UI added noise modulated at 3MHz, see Figure 11 ±44
tC = 7.4ns; clean reference clock, see Figure 11 ±35
tC = 7.4ns with 0.05UI added noise modulated at 3MHz, see Figure 11 ±42
tw High-level output clock pulse duration 4/7 tc ns
tr/f Differential output voltage transition time (tr or tf) See Figure 7 225 500 ps
ten Enable time, SHTDN↑ to phase lock (Yn valid) f(clk) = 135 MHz, See Figure 12 6 µs
tdis Disable time, SHTDN↓ to off-state (CLKOUT high-impedance) f(clk) = 135 MHz, See Figure 13 7 ns
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.